公开(公告)号：US20020000422A1

公开(公告)日：2002-01-03

申请号：US09916734

申请日：2001-07-26

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe ,  Rich Stocks

IPC: C23F001/00 ,  C23F003/00 ,  B44C001/22

CPC classification number: H01J37/321 ,  H01J2237/3345 ,  H01J2237/3347 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76232 ,  Y10S428/901 ,  Y10T428/24479 ,  Y10T428/2457

Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high aspect ratios can be etched.

Abstract translation: 提供了用于蚀刻诸如硅晶片的基板的方法和装置。 在一种具体方法中，衬底组件的表面被图案化的抗蚀剂覆盖以限定待蚀刻的特征。 在这种方法中，然后将表面暴露于等离子体蚀刻器中的等离子体，使得未被抗蚀剂覆盖的表面区域被蚀刻，同时抗蚀剂的厚度增加或蚀刻速率至少比 表面的暴露区域。 该蚀刻工艺可以用常规等离子体蚀刻来进行。 通过将抗蚀剂厚度增加的蚀刻与蚀刻期间抗蚀剂浸透的抗蚀剂的常规蚀刻相结合，可以蚀刻具有高纵横比的特征。