公开(公告)号：US20040262263A1

公开(公告)日：2004-12-30

申请号：US10895502

申请日：2004-07-20

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe ,  Rich Stocks

IPC: C23F001/00

CPC classification number: H01J37/321 ,  H01J2237/3345 ,  H01J2237/3347 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76232 ,  Y10S428/901 ,  Y10T428/24479 ,  Y10T428/2457

Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.

Abstract translation: 提供了用于蚀刻诸如硅晶片的基板的方法和装置。 在一种具体方法中，衬底组件的表面被图案化的抗蚀剂覆盖以限定待蚀刻的特征。 在这种方法中，然后将表面暴露于等离子体蚀刻器中的等离子体，使得未被抗蚀剂覆盖的表面区域被蚀刻，同时抗蚀剂的厚度增加或蚀刻速率至少比 表面的暴露区域。 该蚀刻工艺可以用常规等离子体蚀刻来进行。 通过将蚀刻加强抗蚀剂厚度的蚀刻与蚀刻时的抗蚀剂凹陷的抗蚀剂的常规蚀刻相结合，可以蚀刻具有高纵横比的特征。

公开(公告)号：US20030040186A1

公开(公告)日：2003-02-27

申请号：US10277386

申请日：2002-10-21

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling ,  Kevin G. Donohoe

IPC: H01L021/311

CPC classification number: H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819

Abstract: In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched, and the etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap. In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate. The spaced metal-comprising lines define an uneven surface topology which comprises the lines and a valley between the lines. A layer of second insulative material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the lines and having a gap over the valley. The layer of second insulative material is subjected to an etch which forms a protective material at the bottom of the gap. The protective material substantially prevents the second insulative material from being etched from the bottom of the gap.

Abstract translation: 一方面，本发明包括在不平坦表面拓扑上形成材料的半导体加工方法。 提供具有不平坦表面拓扑的衬底。 不平坦的表面拓扑包括一对向外突出的特征之间的谷。 在不平坦的表面拓扑上形成一层材料。 该层包括在表面拓扑的向外突出的特征之上的向外突出的部分，并在谷的上方具有间隙。 蚀刻该层，并且蚀刻在间隙内形成保护材料，同时移除该层的最外表面。 蚀刻基本上不从间隙的底部去除材料。 在另一方面，本发明包括在含金属线路上形成材料的半导体加工方法。 提供第一绝缘材料基板。 在衬底上形成一对间隔开的金属线。 间隔开的包含金属的线限定了不平坦的表面拓扑，其包括线和线之间的谷。 在不平坦的表面拓扑上形成一层第二绝缘材料。 该层包括在该线上的向外突出的部分并且在该谷的上方具有间隙。 第二绝缘材料层经受在间隙底部形成保护材料的蚀刻。 保护材料基本上防止了第二绝缘材料从间隙的底部被蚀刻。

公开(公告)号：US20020163056A1

公开(公告)日：2002-11-07

申请号：US10188472

申请日：2002-07-02

Applicant: Micron Technology, Inc.

Inventor： Randhir P.S. Thakur ,  Kevin G. Donohoe ,  Zhiqiang Wu ,  Alan R. Reinberg

IPC: H01L029/00

CPC classification number: H01L21/32 ,  H01L21/0332

Abstract: Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

Abstract translation: 通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小机械应力。 通过改变氮化硅中的硅含量来实现分级。 氮化硅可以以基本线性或非线性方式分级。 在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。 在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。 在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小应力。 在另一个实施例中，通过在衬底层上形成氮化硅来降低应力，衬底层又形成在基底层上。

公开(公告)号：US20030041805A1

公开(公告)日：2003-03-06

申请号：US10263624

申请日：2002-10-03

Applicant: Micron Technology, Inc.

Inventor： Guy T. Blalock ,  Kevin G. Donohoe

IPC: C23C016/00

CPC classification number: H01J37/32091 ,  H01J37/321 ,  H01J37/32183 ,  H05H1/46

Abstract: A plasma reactor comprises an electromagnetic energy source coupled to a radiator through first and second variable impedance networks. The plasma reactor includes a chamber having a dielectric window that is proximate to the radiator. A shield is positioned between the radiator and the dielectric window. The shield substantially covers a surface of the radiator near the dielectric window. A portion of the radiator that is not covered by the shield is proximate to a conductive wall of the chamber. Plasma reactor operation includes the following steps. A plasma is ignited in a chamber with substantially capacitive electric energy coupled from the radiator. A variable impedance network is tuned so that the capacitive electric energy coupled into the chamber is diminished. The plasma is then powered with substantially magnetic energy.

公开(公告)号：US20030003755A1

公开(公告)日：2003-01-02

申请号：US09894460

申请日：2001-06-28

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe

IPC: H01L021/302 ,  H01L021/461 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/76224 ,  H01L21/31116 ,  H01L21/76804

Abstract: Plasma etching processes using a plasma containing fluorine as well as bromine and/or iodine are suited for high aspect ratio etching of trenches, contact holes or other apertures in silicon oxide materials. The plasma is produced using at least one fluorine-containing source gas and at least one bromine- or iodine-containing source gas. Bromine/iodine components of the plasma protect the aperture sidewalls from lateral attack by free fluorine, thus advantageously reducing a tendency for bowing of the sidewalls. Ion bombardment suppresses absorption of bromine/iodine components on the etch front, thus facilitating advancement of the etch front without significantly impacting taper.

Abstract translation: 使用含有氟以及溴和/或碘的等离子体蚀刻工艺适用于氧化硅材料中的沟槽，接触孔或其它孔的高纵横比蚀刻。 使用至少一种含氟源气体和至少一种含溴或碘的源气体产生等离子体。 等离子体的溴/碘成分保护孔径侧壁免受游离氟的侧向侵蚀，从而有利地降低侧壁弯曲的倾向。 离子轰击抑制了在蚀刻前沿上的溴/碘成分的吸收，从而便于蚀刻前沿的前进而不会明显地影响锥度。

公开(公告)号：US20020000298A1

公开(公告)日：2002-01-03

申请号：US09922587

申请日：2001-08-03

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe

IPC: H01L021/302

CPC classification number: H01J37/32082 ,  H01J37/32623 ,  H01J37/32642 ,  Y10S156/915

Abstract: This invention is a hardware modification which permits greater uniformity of etching to be achieved in a high-density-source plasma reactor (i.e., one which uses a remote source to generate a plasma, and which also uses high-frequency bias power on the wafer chuck). The invention addresses the uniformity problem which arises as the result of nonuniform power coupling between the wafer and the walls of the etch chamber. The solution to greatly mitigate the nonuniformity problem is to increase the impedance between the wafer and the chamber walls. This may be accomplished by placing a cylindrical dielectric wall around the wafer. Quartz is a dielectric material that is ideal for the cylindrical wall if silicon is to be etched selectively with respect to silicon dioxide, as quartz it is virtually inert under such conditions.

Abstract translation: 本发明是一种硬件修改，其允许在高密度源等离子体反应器（即，使用远程源产生等离子体并且还在晶片上使用高频偏置功率的等离子体反应器）中实现更高的蚀刻均匀性 卡盘）。 本发明解决了由于晶片和蚀刻室的壁之间的不均匀功率耦合而产生的均匀性问题。 大大减轻不均匀性问题的解决方案是增加晶片和室壁之间的阻抗。 这可以通过在晶片周围放置圆柱形介电壁来实现。 石英是一种电介质材料，对于圆柱形壁而言，如果要在二氧化硅上选择性地蚀刻硅，石英是在这种条件下实际上是惰性的。

公开(公告)号：US20040248413A1

公开(公告)日：2004-12-09

申请号：US10888255

申请日：2004-07-09

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe ,  David S. Becker

IPC: H01L021/82 ,  H01L021/302 ,  H01L021/461

CPC classification number: H01L21/76897 ,  C09K13/08 ,  H01L21/31116 ,  H01L21/76802

Abstract: A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous etchant.

Abstract translation: 用各向异性蚀刻半导体衬底的方法使用具有蚀刻选择性碳氟化合物气体的氢氟烃蚀刻气体。 碳氟化合物气体在相对于诸如掺杂或未掺杂的二氧化硅的体电介质材料增强蚀刻停止层的蚀刻选择性的条件下使用。 在一种方法中，在蚀刻停止层上提供二氧化硅介电层，其中蚀刻停止层包括与二氧化硅介电层不同地掺杂的二氧化硅。 提供了包括氢氟烃蚀刻气体和氟碳选择性化合物的气体蚀刻剂，并且将二氧化硅介电层暴露于气体蚀刻剂。

公开(公告)号：US20030062127A1

公开(公告)日：2003-04-03

申请号：US10288047

申请日：2002-11-05

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe

IPC: C23F001/00 ,  C03C015/00 ,  C23C016/00

CPC classification number: H01J37/32082 ,  H01J37/32623 ,  H01J37/32642 ,  Y10S156/915

Abstract: This invention is a hardware modification which permits greater uniformity of etching to be achieved in a high-density-source plasma reactor (i.e., one which uses a remote source to generate a plasma, and which also uses high-frequency bias power on the wafer chuck). The invention addresses the uniformity problem which arises as the result of nonuniform power coupling between the wafer and the walls of the etch chamber. The solution to greatly mitigate the nonuniformity problem is to increase the impedance between the wafer and the chamber walls. This may be accomplished by placing a cylindrical dielectric wall around the wafer. Quartz is a dielectric material that is ideal for the cylindrical wall if silicon is to be etched selectively with respect to silicon dioxide, as quartz it is virtually inert under such conditions.

公开(公告)号：US20020192976A1

公开(公告)日：2002-12-19

申请号：US10217719

申请日：2002-08-13

Applicant: Micron Technology, Inc.

Inventor： Shane J. Trapp ,  Kevin G. Donohoe

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/76224 ,  H01L21/0271 ,  H01L21/3086 ,  Y10T428/24537

Abstract: A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed. The present methods utilize the height difference between the bottom portion of the feature and the surface of the substrate to selectively deposit a self-aligning mask layer relative to a pre-formed opening or other feature, for example, to extend an opening to a depth that an original photomask thickness cannot support.

公开(公告)号：US20020121343A1

公开(公告)日：2002-09-05

申请号：US10132589

申请日：2002-04-25

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Donohoe

IPC: C23F001/00 ,  H01L021/306 ,  H01L021/302 ,  H01L021/461

CPC classification number: H01J37/32082 ,  H01J37/32623 ,  H01J37/32642 ,  Y10S156/915

Abstract: This invention is a hardware modification which permits greater uniformity of etching to be achieved in a high-density-source plasma reactor (i.e., one which uses a remote source to generate a plasma, and which also uses high-frequency bias power on the wafer chuck). The invention addresses the uniformity problem which arises as the result of nonuniform power coupling between the wafer and the walls of the etch chamber. The solution to greatly mitigate the nonuniformity problem is to increase the impedance between the wafer and the chamber walls. This may be accomplished by placing a cylindrical dielectric wall around the wafer. Quartz is a dielectric material that is ideal for the cylindrical wall if silicon is to be etched selectively with respect to silicon dioxide, as quartz it is virtually inert under such conditions.

Abstract translation: 本发明是一种硬件修改，其允许在高密度源等离子体反应器（即，使用远程源产生等离子体并且还在晶片上使用高频偏置功率的等离子体反应器）中实现更高的蚀刻均匀性 卡盘）。 本发明解决了由于晶片和蚀刻室的壁之间的不均匀功率耦合而产生的均匀性问题。 大大减轻不均匀性问题的解决方案是增加晶片和室壁之间的阻抗。 这可以通过在晶片周围放置圆柱形介电壁来实现。 石英是一种电介质材料，对于圆柱形壁而言，如果要在二氧化硅上选择性地蚀刻硅，石英是在这种条件下实际上是惰性的。