-
公开(公告)号：US11922063B2
公开(公告)日：2024-03-05
申请号：US17470594
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F3/0659 , G06F3/0607 , G06F3/0658 , G06F3/0688 , G06F9/30196
Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
-
公开(公告)号：US20230393935A1
公开(公告)日：2023-12-07
申请号：US17807813
申请日：2022-06-20
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm , Scott D. Van De Graaff , Mark D. Ingram , Todd Jackson Plum
CPC classification number: G06F11/1068 , G06F11/0772 , G06F9/30189 , G06F11/3051
Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.
-
公开(公告)号：US20230315599A1
公开(公告)日：2023-10-05
申请号：US18156594
申请日：2023-01-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm , Todd Jackson Plum , Mark D. Ingram , Scott D. Van De Graaff
CPC classification number: G06F11/27 , G06F11/0772 , G06F11/3037
Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. A memory device may include health monitoring logic that is operable to be enabled in a configuration that corresponds to an output, such as an expected output, regardless of a degradation level of the memory device. Such a configuration may be enabled in a mode, such as a test mode, during which the memory device, or a host device coupled with the memory device, or some combination, may evaluate a difference between the output and an actual output of the health monitoring logic. The actual output being the same as the output may provide an indication that at least a portion of the health monitoring logic is functioning properly, and the actual output being different than the output may provide an indication that at least a portion of the health monitoring logic is not functioning properly.
-
公开(公告)号：US20230061144A1
公开(公告)日：2023-03-02
申请号：US17820085
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
Abstract: Methods, systems, and devices for memory operations are described. A read command may be received at a memory device from a host device. As part of an error control operation, a first set of error control bits may be generated for the set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation may be determined. Based on determining the failure of the matching operation, a second set of error control bits that is different than the first set of error control bits may be transmitted to the host device. The second set of error control bits may indicate that the matching operation failed at the memory device.
-
公开(公告)号：US20220237081A1
公开(公告)日：2022-07-28
申请号：US17721462
申请日：2022-04-15
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
-
Patent Agency Ranking
公开(公告)号：US20220197745A1
公开(公告)日：2022-06-23
申请号：US17690772
申请日：2022-03-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.
-
公开(公告)号：US20220066701A1
公开(公告)日：2022-03-03
申请号：US17470594
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
-
公开(公告)号：US11249847B2
公开(公告)日：2022-02-15
申请号：US17216418
申请日：2021-03-29
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
IPC: G06F11/00 , G06F11/10 , H03M13/29 , G11C11/408 , G11C11/4091 , G11C11/22
Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
-
公开(公告)号：US20210350843A1
公开(公告)日：2021-11-11
申请号：US17384013
申请日：2021-07-23
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G11C11/406
Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.
-
公开(公告)号：US20210318928A1
公开(公告)日：2021-10-14
申请号：US17216418
申请日：2021-03-29
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
-
-
-
-
-
-
-
-
-
Search Results
157
records
(took 0.032 seconds)
