公开(公告)号：US20230062701A1

公开(公告)日：2023-03-02

申请号：US17410327

申请日：2021-08-24

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama

IPC: H01L25/065 ,  H01L23/544 ,  H01L25/00 ,  H01L21/50

Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.

公开(公告)号：US11380665B2

公开(公告)日：2022-07-05

申请号：US16553698

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Shiro Uchiyama

IPC: G11C7/02 ,  H01L25/18 ,  H01L25/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/538

Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.

公开(公告)号：US20180301408A1

公开(公告)日：2018-10-18

申请号：US16000697

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： Shiro Uchiyama

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L27/108 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/528 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/10897 ,  H01L29/0649

Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.