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    DYNAMIC SEQUENCING OF DATA PARTITIONS FOR OPTIMIZING MEMORY UTILIZATION AND PERFORMANCE OF NEURAL NETWORKS
    11.
    发明申请
    DYNAMIC SEQUENCING OF DATA PARTITIONS FOR OPTIMIZING MEMORY UTILIZATION AND PERFORMANCE OF NEURAL NETWORKS 有权

    公开(公告)号：US20220147833A1

    公开(公告)日：2022-05-12

    申请号：US17583499

    申请日：2022-01-25

    申请人： Microsoft Technology Licensing, LLC

    发明人： Kent D. CEDOLA ,  Larry Marvin WALL ,  Boris BOBROV ,  George PETRE ,  Chad Balling McBRIDE ,  Amol Ashok AMBARDEKAR

    IPC分类号： G06N3/10 ,  G06F12/02 ,  G06F9/48

    摘要： Optimized memory usage and management is crucial to the overall performance of a neural network (NN) or deep neural network (DNN) computing environment. Using various characteristics of the input data dimension, an apportionment sequence is calculated for the input data to be processed by the NN or DNN that optimizes the efficient use of the local and external memory components. The apportionment sequence can describe how to parcel the input data (and its associated processing parameters—e.g., processing weights) into one or more portions as well as how such portions of input data (and its associated processing parameters) are passed between the local memory, external memory, and processing unit components of the NN or DNN. Additionally, the apportionment sequence can include instructions to store generated output data in the local and/or external memory components so as to optimize the efficient use of the local and/or external memory components.

    REDUCING POWER CONSUMPTION IN A NEURAL NETWORK ENVIRONMENT USING DATA MANAGEMENT
    12.
    发明申请
    REDUCING POWER CONSUMPTION IN A NEURAL NETWORK ENVIRONMENT USING DATA MANAGEMENT 有权

    公开(公告)号：US20210232205A1

    公开(公告)日：2021-07-29

    申请号：US17233379

    申请日：2021-04-16

    申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

    发明人： Amol Ashok AMBARDEKAR ,  Chad Balling MCBRIDE ,  George PETRE ,  Kent D. CEDOLA ,  Larry Marvin WALL

    IPC分类号： G06F1/3234 ,  G06N3/04 ,  G06N3/063

    摘要： Techniques to provide for improved (i.e., reduced) power consumption in an exemplary neural network (NN) and/or Deep Neural Network (DNN) environment using data management. Improved power consumption in the NN/DNN may be achieved by reducing a number of bit flips needed to process operands associated with one or more storages. Reducing the number bit flips associated with the NN/DNN may be achieved by multiplying an operand associated with a first storage with a plurality of individual operands associated with a plurality of kernels of the NN/DNN. The operand associated with the first storage may be neuron input data and the plurality of individual operands associated with the second storage may be weight values for multiplication with the neuron input data. The plurality of kernels may be arranged or sorted and subsequently processed in a manner that improves power consumption in the NN/DNN.

    QUEUE MANAGEMENT FOR DIRECT MEMORY ACCESS
    13.
    发明申请
    QUEUE MANAGEMENT FOR DIRECT MEMORY ACCESS 审中-公开

    公开(公告)号：US20180300634A1

    公开(公告)日：2018-10-18

    申请号：US15702311

    申请日：2017-09-12

    申请人： Microsoft Technology Licensing, LLC

    发明人： Chad Balling McBRIDE ,  Amol Ashok AMBARDEKAR ,  Kent D. CEDOLA ,  George PETRE ,  Larry Marvin Wall ,  Boris BOBROV

    IPC分类号： G06N3/10 ,  G06N3/04 ,  H04L12/715 ,  G06N3/063

    摘要： A direct memory access (DMA) engine may be responsible to enable and control DMA data flow within a computing system. The DMA engine moves blocks of data, associated with descriptors in a plurality of queues, from a source to a destination memory location or address, autonomously from control by a computer system's processor. Based on analysis of the data blocks linked to the descriptors in the queues, the DMA engine and its associated DMA fragmenter ensure that data blocks stored linked to descriptors in the queues do not remain idle for an exorbitant period of time. The DMA fragmenter may divide large data blocks into smaller data blocks to ensure that the processing of large data blocks does not preclude the timely processing of smaller data blocks associated with one or more descriptors in the queues. The data blocks stored may be two-dimensional data blocks.

    POWER-EFFICIENT DEEP NEURAL NETWORK MODULE CONFIGURED FOR PARALLEL KERNEL AND PARALLEL INPUT PROCESSING
    14.
    发明申请
    POWER-EFFICIENT DEEP NEURAL NETWORK MODULE CONFIGURED FOR PARALLEL KERNEL AND PARALLEL INPUT PROCESSING 审中-公开

    公开(公告)号：US20180300615A1

    公开(公告)日：2018-10-18

    申请号：US15951690

    申请日：2018-04-12

    申请人： Microsoft Technology Licensing, LLC

    发明人： Amol Ashok AMBARDEKAR ,  Chad Balling McBRIDE ,  George PETRE ,  Larry Marvin WALL ,  Kent D. CEDOLA ,  Boris BOBROV

    IPC分类号： G06N3/063 ,  G06F1/32

    摘要： A deep neural network (DNN) module utilizes parallel kernel and parallel input processing to decrease bandwidth utilization, reduce power consumption, improve neuron multiplier stability, and provide other technical benefits. Parallel kernel processing enables the DNN module to load input data only once for processing by multiple kernels. Parallel input processing enables the DNN module to load kernel data only once for processing with multiple input data. The DNN module can implement other power-saving techniques like clock-gating (i.e. removing the clock from) and power-gating (i.e. removing the power from) banks of accumulators based upon usage of the accumulators. For example, individual banks of accumulators can be power-gated when all accumulators in a bank are not in use, and do not store data for a future calculation. Banks of accumulators can also be clock-gated when all accumulators in a bank are not in use, but store data for a future calculation.

    ENHANCING PROCESSING PERFORMANCE OF A DNN MODULE BY BANDWIDTH CONTROL OF FABRIC INTERFACE
    16.
    发明申请
    ENHANCING PROCESSING PERFORMANCE OF A DNN MODULE BY BANDWIDTH CONTROL OF FABRIC INTERFACE 审中-公开

    公开(公告)号：US20180299943A1

    公开(公告)日：2018-10-18

    申请号：US15950644

    申请日：2018-04-11

    申请人： Microsoft Technology Licensing, LLC

    发明人： Chad Balling McBRIDE ,  Timothy Hume HEIL ,  Amol Ashok AMBARDEKAR ,  George PETRE ,  Kent D. CEDOLA ,  Larry Marvin WALL ,  Boris BOBROV

    IPC分类号： G06F1/32 ,  G06N3/08

    摘要： An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.

    DATA PROCESSING PERFORMANCE ENHANCEMENT FOR NEURAL NETWORKS USING A VIRTUALIZED DATA ITERATOR
    19.
    发明申请
    DATA PROCESSING PERFORMANCE ENHANCEMENT FOR NEURAL NETWORKS USING A VIRTUALIZED DATA ITERATOR 审中-公开

    公开(公告)号：US20180300633A1

    公开(公告)日：2018-10-18

    申请号：US15694663

    申请日：2017-09-01

    申请人： Microsoft Technology Licensing, LLC

    发明人： Chad Balling MCBRIDE ,  George PETRE ,  Amol Ashok AMBARDEKAR ,  Kent D. CEDOLA ,  Larry Marvin WALL ,  Boris BOBROV

    IPC分类号： G06N3/10

    摘要： The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. Using virtualized hardware iterators, data for processing by the NN/DNN can be traversed and configured to optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, an iterator controller can generate instructions for execution by the NN/DNN representative of one more desired iterator operation types and to perform one or more iterator operations. Data can be iterated according to a selected iterator operation and communicated to one or more neuron processors of the NN/DD for processing and output to a destination memory. The iterator operations can be applied to various volumes of data (e.g., blobs) in parallel or multiple slices of the same volume.