公开(公告)号：US20090251436A1

公开(公告)日：2009-10-08

申请号：US12098093

申请日：2008-04-04

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: G06F3/045 ,  G06F3/038

CPC classification number: G06F1/3203 ,  G06F1/3262 ,  G06F3/038 ,  G06F3/045

Abstract: While taking X-Y coordinate measurements to determine the location of a point of contact on a touch screen, a controller circuit drives the touch screen with a selectable voltage. Voltages output from the touch screen are converted by an ADC into the X-coordinate and Y-coordinate values. The ADC has a convertible input voltage range. If only a low touch screen detection resolution is required, then the voltage with which the touch screen is driven is made to be substantially less than the convertible input voltage range. Only a portion of the convertible input range is usable, but this is adequate for the application and power consumption is reduced. If a higher touch screen detection resolution is required, then the touch screen is driven with a higher voltage. Power consumption is increased, but more or all of the convertible input voltage range of the ADC is then usable.

Abstract translation: 当采取X-Y坐标测量来确定触摸屏上接触点的位置时，控制器电路用可选择的电压来驱动触摸屏。 从触摸屏输出的电压由ADC转换为X坐标和Y坐标值。 ADC具有可转换输入电压范围。 如果仅需要低触摸屏检测分辨率，则使得触摸屏被驱动的电压基本上小于可转换输入电压范围。 只有可转换输入范围的一部分可用，但这对于应用而言是足够的，并且功耗降低。 如果需要更高的触摸屏检测分辨率，则触摸屏将以更高的电压驱动。 功耗增加，但是ADC的可转换输入电压范围的大部分或全部可用。

公开(公告)号：US20090160519A1

公开(公告)日：2009-06-25

申请号：US11962045

申请日：2007-12-20

Applicant: Mustafa Keskin ,  Marzio Pedrali-Noy

Inventor： Mustafa Keskin ,  Marzio Pedrali-Noy

IPC: H03H11/26

CPC classification number: H03K5/131

Abstract: A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.

Abstract translation: 描述了能够提供整数和分数时间分辨率的延迟的可编程延迟电路。 在一个示例性设计中，装置包括第一和第二延迟电路。 第一延迟电路提供整数个时间单位的第一延迟。 第二延迟电路耦合到第一延迟电路并且提供一个时间单位的一小部分的第二延迟。 第一延迟电路可以包括串联耦合的多个单位延迟单元。 每个单元延迟单元可以在启用时提供一个时间单位的延迟。 第二延迟电路可以具有第一和第二路径。 当选择时，第一路径可以提供更短的延迟，并且第二路径可以在选择时提供更长的延迟。 第二路径可以耦合到至少一个虚拟逻辑门，其提供额外的负载以获得用于第二路径的更长的延迟。