公开(公告)号：US11574841B2

公开(公告)日：2023-02-07

申请号：US17004902

申请日：2020-08-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/528

摘要： The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

公开(公告)号：US11792972B2

公开(公告)日：2023-10-17

申请号：US17528505

申请日：2021-11-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H10B12/00

CPC分类号： H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

摘要： A memory array and a method for preparing the memory are provided. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

公开(公告)号：US11557576B2

公开(公告)日：2023-01-17

申请号：US17537972

申请日：2021-11-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L23/495 ,  H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00

摘要： The present application discloses a method for fabricating a semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. method includes providing an active interposer comprising a programmable unit; providing a first logic die and bonding a first side of the active interposer onto the first logic die; providing a first memory die comprising a storage unit; and bonding the first memory die onto a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

公开(公告)号：US11521892B2

公开(公告)日：2022-12-06

申请号：US17334104

申请日：2021-05-28

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L21/762 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/304 ,  H01L21/306 ,  H01L21/8234

摘要： The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.