公开(公告)号：US20220139105A1

公开(公告)日：2022-05-05

申请号：US17431784

申请日：2019-02-22

Applicant: NEC Corporation

Inventor： Yoshimasa ONO ,  Shigeru NAKAMURA ,  Atsufumi SHIBAYAMA ,  Junichi ABA

IPC: G06V40/12 ,  G06V40/13 ,  G06T7/50 ,  G06T7/73 ,  G06T7/13

Abstract: A technique for accurately extracting a fingerprint image for accurate authentication from 3D tomographic luminance data of a finger at a high speed. A processing apparatus (11) according to the present disclosure includes means for, after performing edge detection processing on a tomographic image (101, 102, . . . 10 k, . . . , 10n) at each depth, calculating the total number of edge pixels in the tomographic image from 3D (three-dimensional) tomographic luminance data, and acquiring depth dependence of the number of edges (111, 112), and means for extracting a tomographic image having a striped pattern from the depth dependence of the number of edges and the 3D tomographic luminance data.

公开(公告)号：US20210342102A1

公开(公告)日：2021-11-04

申请号：US17057082

申请日：2019-05-21

Applicant: NEC Corporation

Inventor： Atsufumi SHIBAYAMA ,  Hajime YAMAGIAWA

IPC: G06F3/06 ,  G06F17/14

Abstract: A signal processing apparatus includes a storage processing part that performs storage processing on data represented in a second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted, and an operation processing part that performs operation processing on at least any one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format.

公开(公告)号：US20200372095A1

公开(公告)日：2020-11-26

申请号：US16636832

申请日：2018-08-03

Applicant: NEC CORPORATION

Inventor： Atsufumi SHIBAYAMA

IPC: G06F17/14

Abstract: A fast Fourier transform device includes a data sorting processing unit that includes: a first data sorting unit which input a plurality of first data in a first order and sorting the plurality of first data into a third order; and a second data sorting unit input the plurality of first data in the third order and sorting the plurality of first data into a second order. The first data sorting unit sorts the plurality of first data from the first order into the third order by using, as a unit of transfer, a data set constituted by a prescribed number of data included in the plurality of first data. The second data sorting unit sorts the plurality of first data from the third order into the second order by carrying out sorting among a prescribed number of data included in the data set.

公开(公告)号：US20200304107A1

公开(公告)日：2020-09-24

申请号：US15779568

申请日：2016-12-01

Applicant: NEC Corporation

Inventor： Atsufumi SHIBAYAMA

IPC: H03H17/02 ,  G06F17/15

Abstract: The present invention addresses the problem of increasing the likelihood of making it possible to reduce the consumption of power necessary for filter processing and the amount of heat generated during filter processing. In order to overcome this problem, a second complex signal and a third complex signal are generated from a first complex signal in a frequency domain, the third complex signal being a complex conjugate of the second complex signal. Signal selection is performed from the plurality of types of complex signals having different amounts of change in signal amplitude. Processing is performed on the complex signal selected as the signal using a first filter coefficient and a second filter coefficient. The complex signals after filter processing are synthesized to generate a complex signal, which is then outputted.

公开(公告)号：US20180013409A1

公开(公告)日：2018-01-11

申请号：US15544042

申请日：2016-01-14

Applicant: NEC CORPORATION

Inventor： Atsufumi SHIBAYAMA ,  Junichi ABE ,  Kohei HOSOKAWA

IPC: H03H17/02 ,  G06F17/14

CPC classification number: H03H17/0248 ,  G06F17/14 ,  H03H17/0202 ,  H03H17/0213 ,  H03H2017/0245

Abstract: Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain. This digital filter circuit includes: a separating circuit for separating a first complex number signal, of a frequency domain that was subjected to Fourier transform, into a real number portion and an imaginary number portion; a filter coefficient generating circuit for generating a first frequency domain filter coefficient from a first input filter coefficient and a third input filter coefficient, and for generating a second frequency domain filter coefficient from a second input filter coefficient and the third input filter coefficient; a first filter that filters the separated real number portion using the first frequency domain filter coefficient; a second filter that filters the separated imaginary number portion using the second frequency domain filter coefficient; and a combining circuit for combining the output from the two filters.

公开(公告)号：US20160357706A1

公开(公告)日：2016-12-08

申请号：US15103117

申请日：2014-11-19

Applicant: NEC Corporation

Inventor： Atsufumi SHIBAYAMA

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: [Problem] To provide a fast Fourier transform device that makes it possible to input data to be processed and output a processing result in a desired order. [Solution] A fast Fourier transform device that is provided with: a first transform means that performs a fast Fourier transform or an inverse fast Fourier transform, generates a plurality of pieces of first output data, and outputs the result in a first order; and a first data sorting processing unit that sorts the plurality of pieces of first output data that are output in the first order into a second order in accordance with an output order setting that is based on a first movement amount.

Abstract translation: [问题]提供一种快速傅立叶变换装置，其使得可以输入要处理的数据并以期望的顺序输出处理结果。 解决方案提供一种快速傅里叶变换装置，其具有执行快速傅里叶变换或快速傅里叶逆变换的第一变换装置，产生多条第一输出数据，并以一级输出结果; 以及第一数据排序处理单元，其根据基于第一移动量的输出顺序设置将按照第一顺序输出的多个第一输出数据分成二阶。

公开(公告)号：US20250054208A1

公开(公告)日：2025-02-13

申请号：US18926835

申请日：2024-10-25

Applicant: NEC Corporation

Inventor： Yoshimasa ONO ,  Shigeru NAKAMURA ,  Atsufumi SHIBAYAMA ,  Junichi ABE

IPC: G06T11/00 ,  G06F21/32 ,  G06T15/04 ,  G06T15/08 ,  G06V40/12 ,  G06V40/13

Abstract: Provided is a processing apparatus capable of obtaining a 2D image from 3D tomographic images, extracting an image for accurate authentication, and extracting an image at a high speed. A processing apparatus includes: means for calculating, from three-dimensional luminance data indicating an authentication target, depth dependence of striped pattern sharpness in a plurality of regions on a plane perpendicular to a depth direction of the target; means for calculating a depth at which the striped pattern sharpness is the greatest in the depth dependence of striped pattern sharpness; rough adjustment means for correcting the calculated depth on the basis of depths of other regions positioned respectively around the plurality of regions; fine adjustment means for selecting a depth closest to the corrected depth and at which the striped pattern sharpness is at an extreme; and means for extracting an image with a luminance on the basis of the selected depth.

公开(公告)号：US20250028351A1

公开(公告)日：2025-01-23

申请号：US18760422

申请日：2024-07-01

Applicant: NEC Corporation

Inventor： Atsufumi SHIBAYAMA

IPC: G06F1/08 ,  H03K23/66

Abstract: A processing device according to an aspect of the present disclosure includes: a toggle signal reception circuit configured to receive a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and a communication circuit configured to communicate with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.

公开(公告)号：US20230082433A1

公开(公告)日：2023-03-16

申请号：US17802251

申请日：2021-03-26

Applicant: NEC Corporation

Inventor： Atsufumi SHIBAYAMA

IPC: G06F17/14

Abstract: A fast Fourier transform device comprises: a first transform means including a first butterfly computation processing means that performs butterfly computation processing and outputs a plurality of sets of first output data in a first order; and a first data rearrangement processing means. The first butterfly computation processing means includes a plurality of radix-n butterfly computation processing means (where n is a multiple of 2), the number of the plurality of radix-n butterfly computation processing means being more than or equal to the number of the plurality of sets, and the plurality of sets of the first output data are output in the first order from the plurality of radix-n butterfly computation processing means.

公开(公告)号：US20220309123A1

公开(公告)日：2022-09-29

申请号：US17701951

申请日：2022-03-23

Applicant: NEC Corporation

Inventor： Atsufumi SHIBAYAMA

IPC: G06F17/14

Abstract: A fast Fourier transform device according to the present disclosure includes a data sorting unit that sorts N (N is an integer) number of first input data in a first order and outputs N number of first output data in a second order, a twiddle multiplication unit that performs twiddle multiplication that multiplies the N number of first output data by a twiddle factor, and outputs the N number of first output data in the second order, and a butterfly computation unit that performs butterfly computation on the N number of first output data and outputs N number of second output data in the second order, wherein the second order is an order where N number of second output data X(k) and X(N−k) have a time lag of one cycle or less, and a bit transition rate between consecutive cycles of the twiddle factor is small.