公开(公告)号：US20230384341A1

公开(公告)日：2023-11-30

申请号：US18323969

申请日：2023-05-25

申请人： Robert Bosch GmbH

发明人： Timo Heikkilä ,  Rui Zhang

IPC分类号： G01P7/00 ,  H03H17/02

CPC分类号： G01P7/00 ,  H03H17/0202 ,  H03H2017/0205

摘要： A method for evaluating sensor data. In the method, firstly, raw sensor data and/or processed sensor data from at least one sensor are input and measurement data determined from the raw sensor data and/or the processed sensor data. The measurement data are then corrected on the basis of a mathematical model, wherein, on correction, drift of the raw sensor data and/or of the processed sensor data is determined and removed from the measurement data. The corrected measurement data are furthermore output.

公开(公告)号：US20180013409A1

公开(公告)日：2018-01-11

申请号：US15544042

申请日：2016-01-14

申请人： NEC CORPORATION

发明人： Atsufumi SHIBAYAMA ,  Junichi ABE ,  Kohei HOSOKAWA

IPC分类号： H03H17/02 ,  G06F17/14

CPC分类号： H03H17/0248 ,  G06F17/14 ,  H03H17/0202 ,  H03H17/0213 ,  H03H2017/0245

摘要： Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain. This digital filter circuit includes: a separating circuit for separating a first complex number signal, of a frequency domain that was subjected to Fourier transform, into a real number portion and an imaginary number portion; a filter coefficient generating circuit for generating a first frequency domain filter coefficient from a first input filter coefficient and a third input filter coefficient, and for generating a second frequency domain filter coefficient from a second input filter coefficient and the third input filter coefficient; a first filter that filters the separated real number portion using the first frequency domain filter coefficient; a second filter that filters the separated imaginary number portion using the second frequency domain filter coefficient; and a combining circuit for combining the output from the two filters.

公开(公告)号：US20170338802A1

公开(公告)日：2017-11-23

申请号：US15519823

申请日：2014-12-01

申请人： HARBIN ENGINEERING UNIVERSITY

发明人： Yuxin Zhao ,  Chang Liu ,  Harbin, Heilongjiang Zhang ,  Liqiang Liu ,  Gang Li ,  Feng Gao ,  Ning Li ,  Zhifeng Shen ,  Zhenxing Zhang ,  Zhao Qi

IPC分类号： H03H17/02

CPC分类号： H03H17/0282 ,  G06F17/50 ,  H03H17/0202 ,  H03H2017/021

摘要： The present invention provides an actually-measured marine environment data assimilation method based on sequence recursive filtering three-dimensional variation. The method includes: preprocessing actually-measured marine environment data; calculating a target function value; calculating a gradient value of a target function; calculating a minimum value of the target function; extracting space multi-scale information from the actually-measured data; and updating background field data to form a final data assimilation analysis field. The present invention improves the traditional recursive filtering three-dimensional variation method, and sequentially assimilates information with different scales, thereby effectively overcoming the problem that multi-scale information cannot be effectively extracted by a traditional three-dimensional variation method. A high-order recursive Gaussian filter is used, and a cascaded form of the high-order recursive filter is converted into a parallel structure, so that the recursive filtering process of the recursive Gaussian filter can be executed in parallel, and many problems caused by a cascaded filter are overcome.

公开(公告)号：US09025711B2

公开(公告)日：2015-05-05

申请号：US13965375

申请日：2013-08-13

申请人： Applied Micro Circuits Corporation

发明人： Moshe Malkin

IPC分类号： H04B1/10 ,  H04L27/06 ,  G06F17/15 ,  H04B1/12 ,  H04B1/38

CPC分类号： H03H17/0202 ,  H03H17/0213

摘要： Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels.

摘要翻译： 介绍了收发器快速滤波技术。 多维滤波处理器组件（MDFPC）可以执行收发器的多个数字滤波器的配置和调整。 MDFPC可以将收发器的多个单独的滤波器作为单个更大的多维滤波器来处理，并且在单个适配操作中联合更新多个滤波器，而不是在多个滤波器上执行多个适配操作。 为了便于多维滤波器适配，MDFPC可以管理与滤波器的输入相关联的相互交叉相关。 MDFPC可以通过在频域中执行多维滤波器适配来促进多维滤波器适应，其中可以针对多个频率子信道并行执行自适应。 对于每个频率子信道，MDFPC可以执行滤波器适配，其中可以为各个频率子信道生成各自的滤波器适配矩阵以执行更新以便于管理与不同频率子信道相关联的不同交叉相关。

公开(公告)号：US20140379771A1

公开(公告)日：2014-12-25

申请号：US14364774

申请日：2012-10-26

申请人： Atsufumi Shibayama ,  Junichi Abe

发明人： Atsufumi Shibayama ,  Junichi Abe

IPC分类号： H03H17/02

CPC分类号： H03H17/0213 ,  H03H17/0202 ,  H03H17/0248 ,  H03H2218/04

摘要： A digital filter circuit includes an FFT circuit (13) that transforms a complex signal in a time domain into a signal in a frequency domain, an I/Q separation circuit (15) that separates the signal in the frequency domain into a signal in a first frequency domain that corresponds to the real part of the complex signal in the time domain, and a signal in a second frequency domain that corresponds to the imaginary part of the complex signal in the time domain, a filter circuit (21) that performs filter processing on the signal in the first frequency domain, a filter circuit (22) that performs filter processing on the signal in the second frequency domain, an I/Q combination circuit (16) that combines an output from the filter circuit (21) and an output from the filter circuit (22) to generate a signal in a third frequency domain, a filter circuit (23) that performs filter processing on the signal in the third frequency domain, and an IFFT circuit (14) that transforms an output signal from the filter circuit (23) into a signal in the time domain.

摘要翻译： 数字滤波电路包括将时域中的复信号变换成频域的信号的FFT电路（13），将频域中的信号分离为频域的信号的I / Q分离电路（15） 对应于时域中的复信号的实部的第一频域和对应于时域中的复信号的虚部的第二频域中的信号，执行滤波器的滤波器电路（21） 对第一频域中的信号进行处理，对第二频域中的信号进行滤波处理的滤波器电路（22），组合来自滤波器电路（21）的输出的I / Q组合电路（16）和 来自滤波器电路（22）的输出以产生第三频域中的信号，对第三频域中的信号执行滤波处理的滤波器电路（23），以及IFFT电路（14），其将输出信号 来了 将滤波器电路（23）转换成时域中的信号。

公开(公告)号：US20130097212A1

公开(公告)日：2013-04-18

申请号：US13274129

申请日：2011-10-14

申请人： Mike M. Cai ,  Huiming Zhang

发明人： Mike M. Cai ,  Huiming Zhang

IPC分类号： G06F17/10 ,  G06F7/00

CPC分类号： H03H17/0202 ,  G06F17/10 ,  G06F17/153 ,  H03H2017/0245

摘要： Disclosed are new approaches to Multi-dimensional filtering with a reduced number of memory reads and writes. In one embodiment, a filter includes first and second coefficients. A block of a data having width and height each equal to the number of one of the first or second coefficients is read from a memory device. Arrays of values from the block are filtering using the first filter coefficients and the results filtered using the second coefficients. The final result may be optionally blended with another data value and written to a memory device. Registers store results of filtering with the first coefficients. The block of data may be read from a location including a source coordinate. The final result of filtering may be written to a destination coordinate obtained by rotating and/or mirroring the source coordinate. The orientation of arrays filtered using the first coefficients varies according to a rotation mode.

摘要翻译： 公开了具有减少的存储器读取和写入数量的多维过滤的新方法。 在一个实施例中，滤波器包括第一和第二系数。 从存储器件读取具有各自等于第一或第二系数中的一个的数量的宽度和高度的数据块。 来自块的值的数组使用第一滤波器系数进行滤波，并且使用第二系数滤波结果。 最终结果可以可选地与另一数据值混合并写入存储器件。 寄存器存储具有第一系数的滤波结果。 可以从包括源坐标的位置读取数据块。 滤波的最终结果可以写入通过旋转和/或镜像源坐标获得的目的地坐标。 使用第一系数滤波的阵列的取向根据旋转模式而变化。

公开(公告)号：US07298854B2

公开(公告)日：2007-11-20

申请号：US10309518

申请日：2002-12-04

申请人： Walid K. M. Ahmed

发明人： Walid K. M. Ahmed

IPC分类号： H04B15/00 ,  H04R1/40

CPC分类号： H03H17/0202 ,  H03F2200/504

摘要： Apparatus, methods and articles of manufacture are disclosed for modifying electromagnetic waves by reducing noise in those waves. A transfer function for a plurality of segments is derived through identifying a desired output parameter. That transfer function is then applied, via a plurality of filters or other devices, to a wave, in order to achieve said transfer function.

摘要翻译： 公开了用于通过降低这些波中的噪声来修改电磁波的装置，方法和制品。 通过识别期望的输出参数导出多个段的传递函数。 然后，通过多个滤波器或其他装置将该传递函数应用于波，以实现所述传递函数。

公开(公告)号：US20020184276A1

公开(公告)日：2002-12-05

申请号：US09823390

申请日：2001-03-30

发明人： Tinku Acharya

IPC分类号： G06K009/40 ,  G06F017/10 ,  G06T005/00

CPC分类号： H03H17/0202

摘要： Embodiments of a two-dimensional pyramid filter architecture are described.

公开(公告)号：US06377968B1

公开(公告)日：2002-04-23

申请号：US09291956

申请日：1999-04-15

申请人： Junko Nakase ,  Takashi Nakamoto

发明人： Junko Nakase ,  Takashi Nakamoto

IPC分类号： G06F1710

CPC分类号： H03H17/0202 ,  H04N9/64

摘要： There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit includes a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

摘要翻译： 提供了一种滤波电路，其电路规模小，适用于其中定期插入或复用亮度信号Y和色差信号Cb和Cr的数据的数字数据串。 数字滤波电路包括由多个D触发器组成的延迟线，该D触发器与数据串的频率一起工作，其中亮度信号Y和色差信号Cb和Cr被有规律地插入或复用为多个乘法器 用于将所述延迟线的多个抽头乘以相应的系数;以及加法器，用于相加所述乘法器的输出，其中连接到乘法器的抽头由选择器切换。 它允许使用一个数字滤波电路来以时分方式处理信号Y，Cb和Cr，以实现使用较少乘法器和加法器并且其电路规模小的数字滤波电路。

公开(公告)号：US5933545A

公开(公告)日：1999-08-03

申请号：US756120

申请日：1996-11-25

申请人： Farid Kazi ,  Alain Pirson

发明人： Farid Kazi ,  Alain Pirson

IPC分类号： H04N7/26 ,  G06T3/40 ,  H03H17/02 ,  H04N5/14 ,  G06K9/36

CPC分类号： H04N5/14 ,  H03H17/0202

摘要： A decimation device for digital data sequences includes a multiplexer mounted in cascade with a calculator producing, alternately, during a first calculation cycle, the mean M.sub.i of at least two data sequences representing the pixels P(i,j) and P(i,j+1) in a line L.sub.i, and during a following calculation cycle, the mean M.sub.c. The mean M.sub.c is composed of the mean M.sub.i and of an intermediate sequence previously calculated and stored in a storage register arranged between an output for the calculation stage and at least one of the inputs to the multiplexer. The intermediate sequence represents the mean M.sub.i-1 of at least two data sequences representing pixels P(i-1,j) and P(i-1,j+1) in a line L.sub.i-1, where i varies from 0 to N-1 and j varies from 0 to M-1.

摘要翻译： 用于数字数据序列的抽取装置包括与计算器级联的多路复用器，交替地在第一计算周期期间产生表示像素P（i，j）和P（i，j）的至少两个数据序列的平均值 +1）在一行中，在下一个计算周期中，平均值为Mc。 平均值Mc由平均值Mi和先前计算并存储在布置在计算阶段的输出和多路复用器的至少一个输入之间的存储寄存器中的中间序列组成。 中间序列表示线路Li-1中表示像素P（i-1，j）和P（i-1，j + 1）的至少两个数据序列的平均值Mi-1，其中i从0变化到N -1和j从0到M-1变化。