公开(公告)号：US20200293317A1

公开(公告)日：2020-09-17

申请号：US16762317

申请日：2018-11-09

Applicant: NEC Corporation

Inventor： Yuki KOBAYASHI

IPC: G06F9/30 ,  G06F9/32

Abstract: A data processing device according to the present invention includes: a loop counter group that includes a loop-control register set; a loop controller that controls the loop counter group, based on a value of the loop counter group, and generates a loop end signal; a controller that controls the loop counter group and the loop controller, based on an instruction word taken from an instruction memory and the loop end signal, and generates a calculator control signal and a program-counter control signal; a calculator that executes a calculation, based on the calculator control signal; and a program counter that performs a count operation in response to the program-counter control signal, and stores an address of the instruction memory storing an instruction word to be executed next.

公开(公告)号：US20230376559A1

公开(公告)日：2023-11-23

申请号：US18027280

申请日：2020-11-02

Applicant: NEC Corporation

Inventor： Yuki KOBAYASHI ,  Fumiyo Takano ,  Hiroaki Inoue ,  Takuya Araki ,  Motol Suzuki ,  Takahiro Nishimura ,  Hiroshi Chishima ,  Akihiro Yatabe

IPC: G06F17/11

CPC classification number: G06F17/11

Abstract: The feature information derivation means 72 derives feature information that represents a feature of a model used to solve a combinatorial optimization problem, when the model is given. The solution method selection means 73 selects a solution method for the combinatorial optimization problem from among predetermined multiple types of solution methods based on the feature information. The solution request means 74 send a solution request that includes information that can specify the model used to solve the combinatorial optimization problem to a solution device that solves the combinatorial optimization problem using the selected solution method.

公开(公告)号：US20190042389A1

公开(公告)日：2019-02-07

申请号：US16073875

申请日：2017-01-31

Applicant: NEC Corporation

Inventor： Yuki KOBAYASHI

IPC: G06F11/34 ,  G06F17/50

Abstract: A design assistance method executed by a design assistance device for a computer system including a CPU and an accelerator, the design assistance method includes: extracting, from an input program described in a high-level language, a process including a function and data including a variable, and analyzing a relationship between a process and data, the relationship including an amount of access from the process to the data, based on a number of times of execution of the function or a loop; evaluating, for the acquired process, a used amount of resource, a delay, and a communication band of the accelerator, based on a hardware specification; and generating, for the acquired process and data, candidates represented by a combination of allocations to the CPU and the accelerator, and acquiring and presenting, for each of the candidates, a used amount of resource, a communication band, and performance of the input program.