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    SOLUTION ACCURACY GUARANTEEING ANNEALING CALCULATION DEVICE, METHOD, AND PROGRAM
    1.
    发明公开
    SOLUTION ACCURACY GUARANTEEING ANNEALING CALCULATION DEVICE, METHOD, AND PROGRAM 审中-公开

    公开(公告)号：US20230289401A1

    公开(公告)日：2023-09-14

    申请号：US18013416

    申请日：2020-07-03

    Applicant: NEC Corporation

    Inventor： Hiroaki Inoue ,  Takuya Araki ,  Motoi Suzuki ,  Fumiyo Takano ,  Yuki Kobayashi ,  Hiroshi Chishima ,  Akihiro Yatabe ,  Takahiro Nishimura

    IPC: G06F17/18

    CPC classification number: G06F17/18

    Abstract: A solution accuracy guaranteeing annealing calculation device includes a first solving unit which solves a combinatorial optimization problem by an annealing method, and a second solving unit which solves a relaxation problem, which is a problem generated by relaxing constraints imposed on the combinatorial optimization problem, wherein the second solving unit calculates, if the combinatorial optimization problem is a minimization problem, a lower bound of a minimization target in the minimization problem by solving the relaxation problem generated from the combinatorial optimization problem, and calculates, if the combinatorial optimization problem is a maximization problem, an upper bound of a maximization target in the maximization problem by solving the relaxation problem generated from the combinatorial optimization problem.

    Area allocation device, area allocation method, and non-volatile recording medium
    3.
    发明授权
    Area allocation device, area allocation method, and non-volatile recording medium 有权

    公开(公告)号：US12019603B2

    公开(公告)日：2024-06-25

    申请号：US16338741

    申请日：2017-10-10

    Applicant: NEC Corporation

    Inventor： Takuya Araki

    IPC: G06F16/00 ,  G06F12/02 ,  G06F16/22 ,  G06N20/00

    CPC classification number: G06F16/2237 ,  G06F12/0207 ,  G06F16/2264 ,  G06N20/00

    Abstract: Provided are an area allocation device and the like that can efficiently allocate memory volume for processing of matrix operations. The area allocation device specifies array identifiers representing positions of elements storing a value different from a predetermined value in each array of subarray information in array information, arrays consisting of a plurality of element, the array information including a plurality of information representing the arrays, the subarray information corresponding to at least a part of the arrays; calculates a number of the specified array identifiers; and allocates a memory area having a memory volume depending the calculated number.

    SOLUTION METHOD SELECTION DEVICE AND METHOD
    5.
    发明公开
    SOLUTION METHOD SELECTION DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230376559A1

    公开(公告)日：2023-11-23

    申请号：US18027280

    申请日：2020-11-02

    Applicant: NEC Corporation

    Inventor： Yuki KOBAYASHI ,  Fumiyo Takano ,  Hiroaki Inoue ,  Takuya Araki ,  Motol Suzuki ,  Takahiro Nishimura ,  Hiroshi Chishima ,  Akihiro Yatabe

    IPC: G06F17/11

    CPC classification number: G06F17/11

    Abstract: The feature information derivation means 72 derives feature information that represents a feature of a model used to solve a combinatorial optimization problem, when the model is given. The solution method selection means 73 selects a solution method for the combinatorial optimization problem from among predetermined multiple types of solution methods based on the feature information. The solution request means 74 send a solution request that includes information that can specify the model used to solve the combinatorial optimization problem to a solution device that solves the combinatorial optimization problem using the selected solution method.

    Parallel union control device, parallel union control method, and storage medium
    7.
    发明授权
    Parallel union control device, parallel union control method, and storage medium 有权

    公开(公告)号：US11200056B2

    公开(公告)日：2021-12-14

    申请号：US16967866

    申请日：2019-02-05

    Applicant: NEC CORPORATION

    Inventor： Harumichi Yokoyama ,  Takuya Araki ,  Haoran Li

    IPC: G06F16/2453 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

    Abstract: A parallel union control device includes: at least one memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause each of the plurality of arithmetic units included in an parallel computer including a vector register to: successively compare input elements of a pair of input sets to undergo union processing, the pair being stored in an input operand register in the vector register; select one of the input elements as an output element of an output set, based on a comparison result; and store the output element into an output operand register in the vector register; shift a pointer pointing to the input element; load the input sets into the input operand register from a memory; store the output sets into the memory from the output operand register; and determine whether union processing performed in parallel is ended.

    Information processing device, data processing method therefor, and recording medium
    9.
    发明授权
    Information processing device, data processing method therefor, and recording medium 有权

    公开(公告)号：US11423054B2

    公开(公告)日：2022-08-23

    申请号：US16131311

    申请日：2018-09-14

    Applicant: NEC Corporation

    Inventor： Takuya Araki

    IPC: G06F16/28 ,  G06F16/23 ,  G06F16/24 ,  G06F16/583 ,  G06F16/22

    Abstract: An information processing device includes: a feature quantity obtaining unit which obtains a feature quantity of an object to be extracted, which is extracted from a retrieval target, and specific information to be specified an appearing location of it; a feature quantity holding unit which, when storing the feature quantity in a feature quantity table, adds new identification information to the feature quantity and holds the feature quantity in the feature quantity table when a similar feature quantity in which a similarity with the feature quantity is no less than a threshold is not included in the feature quantity table, and outputs identification information of the similar feature quantity as identification information of the feature quantity when the similar feature quantity is included in the feature quantity table; and a retrieval table holding unit which holds the specific information associated with the added identification information or the outputted identification information.

    Sparse matrix standardization device, sparse matrix standardization method, sparse matrix standardization program, and data structure
    10.
    发明授权
    Sparse matrix standardization device, sparse matrix standardization method, sparse matrix standardization program, and data structure 有权

    公开(公告)号：US12299067B2

    公开(公告)日：2025-05-13

    申请号：US17298291

    申请日：2018-12-05

    Applicant: NEC Corporation

    Inventor： Takuya Araki

    IPC: G06F17/16 ,  G06F7/499 ,  G06F17/18 ,  G06N3/08

    Abstract: A computation unit 11 performs, for each column of a target matrix to be standardized, a computation process to compute the average and standard deviation of the value of each component of the column. A first dividing unit 12 performs, for each column of the target matrix, a first dividing process to divide the value of each component of the column by the standard deviation computed based on the column. A second dividing unit 13 performs, for each column of the target matrix, a second dividing process to divide the average computed based on the column by the standard deviation computed based on the column. A generation unit 14 which arranges the quotients computed by a plurality of second dividing processes, in a row in the order of the columns of the target matrix from which the quotients are computed, thereby generating a row vector.

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