公开(公告)号：US09435861B2

公开(公告)日：2016-09-06

申请号：US13663379

申请日：2012-10-29

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract translation: 介绍了锁存器的系统和方法。 在一个实施例中，系统包括传播组件，数据传播组件和控制组件中的扫描。 传播分量中的扫描可操作以在数值扫描和再循环值之间进行选择。 数据传播组件可操作以在数据值和从传播组件中的扫描转发的结果之间进行选择，其中数据传播组件的结果作为再循环值被转发到传播组件中的扫描。 控制组件可操作以通过传播组件和数据传播组件中的扫描来控制选择的指示。

公开(公告)号：US20150263708A1

公开(公告)日：2015-09-17

申请号：US14723356

申请日：2015-05-27

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

公开(公告)号：US20140125393A1

公开(公告)日：2014-05-08

申请号：US14151715

申请日：2014-01-09

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  William J. Dally ,  Jonah M. Alben

IPC: H03K3/356

CPC classification number: H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Abstract translation: 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。