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公开(公告)号：US20240303076A1
公开(公告)日：2024-09-12
申请号：US18377718
申请日：2023-10-06
Applicant: NVIDIA Corporation
Inventor： Brent Ralph Boswell , Ming Y. Siu , Jack H. Choquette , Jonah M. Alben , Stuart Oberman
CPC classification number: G06F9/30014 , G06F9/3001 , G06F9/30036 , G06F9/3012 , G06F9/3851 , G06T1/20
Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
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公开(公告)号：US20220391206A1
公开(公告)日：2022-12-08
申请号：US17890540
申请日：2022-08-18
Applicant: NVIDIA Corporation
Inventor： Brent Ralph Boswell , Ming Y. Siu , Jack H. Choquette , Jonah M. Alben , Stuart Oberman
Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
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公开(公告)号：US11275662B2
公开(公告)日：2022-03-15
申请号：US17143968
申请日：2021-01-07
Applicant: NVIDIA Corporation
Inventor： Jonah M. Alben , Sachin Satish Idgunji , Jue Wu
IPC: G06F11/263 , G06F11/22 , G01R31/3177 , G06F1/12 , G06T1/20 , G06F1/10 , G11C11/409 , H03K3/037
Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.
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公开(公告)号：US20210157699A1
公开(公告)日：2021-05-27
申请号：US17143968
申请日：2021-01-07
Applicant: NVIDIA Corporation
Inventor： Jonah M. Alben , Sachin Satish Idgunji , Jue Wu
IPC: G06F11/263 , G06F11/22 , G01R31/3177 , G06F1/12 , G06T1/20 , G06F1/10
Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.
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公开(公告)号：US10338919B2
公开(公告)日：2019-07-02
申请号：US15826435
申请日：2017-11-29
Applicant: NVIDIA Corporation
Inventor： Brent Ralph Boswell , Ming Y. Siu , Jack H. Choquette , Jonah M. Alben , Stuart Oberman
Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20170323475A1
公开(公告)日：2017-11-09
申请号：US15147872
申请日：2016-05-05
Applicant: NVIDIA Corporation
Inventor： Henry Packard Moreton , Jonah M. Alben
CPC classification number: G06T15/80 , G06T15/20 , G06T15/30 , G06T2215/06
Abstract: A system, method, and computer program product are provided for rendering at variable sampling rates. Vertex coordinates for 3D primitive are received from a shader execution unit, and an arithmetic operation is performed on the vertex coordinates by fixed operation circuitry to produce modified vertex coordinates in homogeneous coordinate space. The modified vertex coordinates are transformed from homogeneous coordinate space into screen-space to produce screen-space vertex coordinates of a transformed 3D primitive and the transformed 3D primitive is rasterized in screen-space using the screen-space vertex coordinates to produce an image for display.
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公开(公告)号：US20140125393A1
公开(公告)日：2014-05-08
申请号：US14151715
申请日：2014-01-09
Applicant: NVIDIA Corporation
Inventor： Ilyas Elkin , William J. Dally , Jonah M. Alben
IPC: H03K3/356
CPC classification number: H03K3/356 , H03K3/356026 , H03K3/356052 , H03K3/356147 , H03K3/356191
Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.
Abstract translation: 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。
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公开(公告)号：US11816482B2
公开(公告)日：2023-11-14
申请号：US17890706
申请日：2022-08-18
Applicant: NVIDIA Corporation
Inventor： Brent Ralph Boswell , Ming Y. Siu , Jack H. Choquette , Jonah M. Alben , Stuart Oberman
CPC classification number: G06F9/30014 , G06F9/3001 , G06F9/3012 , G06F9/30036 , G06F9/3851 , G06T1/20
Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
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公开(公告)号：US20220405098A1
公开(公告)日：2022-12-22
申请号：US17890706
申请日：2022-08-18
Applicant: NVIDIA Corporation
Inventor： Brent Ralph Boswell , Ming Y. Siu , Jack H. Choquette , Jonah M. Alben , Stuart Oberman
Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
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公开(公告)号：US20220156169A1
公开(公告)日：2022-05-19
申请号：US17591481
申请日：2022-02-02
Applicant: NVIDIA Corporation
Inventor： Jonah M. Alben , Sachin Satish Idgunji , Jue Wu
IPC: G06F11/263 , G06F11/22 , G01R31/3177 , G06F1/12 , G06T1/20 , G06F1/10
Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.
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