公开(公告)号：US10121220B2

公开(公告)日：2018-11-06

申请号：US14698024

申请日：2015-04-28

Applicant: Nvidia Corporation

Inventor： Jeffrey Bolz

IPC: G06T1/20 ,  G06F12/0831 ,  G06T1/60 ,  G09G5/395 ,  G06F9/38 ,  G06T15/04 ,  G06T15/00

Abstract: A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases.

公开(公告)号：US10055806B2

公开(公告)日：2018-08-21

申请号：US14924618

申请日：2015-10-27

Applicant: NVIDIA CORPORATION

Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

公开(公告)号：US09727392B2

公开(公告)日：2017-08-08

申请号：US14856468

申请日：2015-09-16

Applicant: NVIDIA Corporation

Inventor： Jeffrey Bolz

IPC: G06F13/00 ,  G06F9/54

CPC classification number: G06F9/54

Abstract: Techniques for passing dependencies in an application programming interface API includes identifying a plurality of passes of execution commands. For each set of passes, wherein one pass is a destination pass and the other pass is a source pass to each other, one or more dependencies, of one or more dependency types, are determined between the execution commands of the destination pass and the source pass. Pass objects are then created for each identified pass, wherein each pass object records the execution commands and dependencies between the corresponding destination and source passes.