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    Techniques for maintaining atomicity and ordering for pixel shader operations
    11.
    发明授权
    Techniques for maintaining atomicity and ordering for pixel shader operations 有权

    公开(公告)号：US10453168B2

    公开(公告)日：2019-10-22

    申请号：US15999185

    申请日：2018-08-17

    Applicant: NVIDIA Corporation

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

    Techniques for maintaining atomicity and ordering for pixel shader operations
    12.
    发明授权
    Techniques for maintaining atomicity and ordering for pixel shader operations 有权

    公开(公告)号：US10055806B2

    公开(公告)日：2018-08-21

    申请号：US14924618

    申请日：2015-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

    System, method, and computer program product for accessing multi-sample surfaces
    13.
    发明授权
    System, method, and computer program product for accessing multi-sample surfaces 有权
    用于访问多样品表面的系统，方法和计算机程序产品

    公开(公告)号：US09436971B2

    公开(公告)日：2016-09-06

    申请号：US13970542

    申请日：2013-08-19

    Applicant: NVIDIA Corporation

    Inventor： Jeffrey Alan Bolz ,  Patrick R. Brown ,  Tyson Bergland ,  Alexander Lev Minkin

    IPC: G06T11/40 ,  G06T1/60 ,  G06T5/00

    CPC classification number: G06T1/60 ,  G06T5/002 ,  G06T11/40

    Abstract: A system, method, and computer program product are provided for accessing multi-sample surfaces. A multi-sample store instruction that specifies data for a single sample of a multi-sample pixel and a sample mask is received and the data for the single sample is stored to each sample of the multi-sample pixel that is enabled according to the sample mask. A multi-sample load instruction that specifies a multi-sample pixel is received, and, in response to executing the multi-sample load instruction, data for one sample of the multi-sample pixel is received. A determination is made that the data for the one sample of the multi-sample pixel represents multi-sample pixel data for at least one additional sample of the multi-sample pixel.

    Abstract translation: 提供了用于访问多样本表面的系统，方法和计算机程序产品。 接收多样本存储指令，指定多样本像素和样本掩模的单个样本的数据，并将单个样本的数据存储到根据样本启用的多样本像素的每个样本 面具。 接收指定多样本像素的多样本加载指令，并且响应于执行多样本加载指令，接收多样本像素的一个样本的数据。 确定多样本像素的一个样本的数据表示多样本像素的至少一个附加样本的多样本像素数据。

    Techniques for maintaining atomicity and ordering for pixel shader operations
    14.
    发明申请
    Techniques for maintaining atomicity and ordering for pixel shader operations 审中-公开

    公开(公告)号：US20180374185A1

    公开(公告)日：2018-12-27

    申请号：US15999185

    申请日：2018-08-17

    Applicant: NVIDIA Corporation

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

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