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    Techniques for maintaining atomicity and ordering for pixel shader operations
    1.
    发明授权
    Techniques for maintaining atomicity and ordering for pixel shader operations 有权

    公开(公告)号：US10032245B2

    公开(公告)日：2018-07-24

    申请号：US14924628

    申请日：2015-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T1/60

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

    Techniques for maintaining atomicity and ordering for pixel shader operations
    2.
    发明授权
    Techniques for maintaining atomicity and ordering for pixel shader operations 有权

    公开(公告)号：US10453168B2

    公开(公告)日：2019-10-22

    申请号：US15999185

    申请日：2018-08-17

    Applicant: NVIDIA Corporation

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

    Techniques for maintaining atomicity and ordering for pixel shader operations
    3.
    发明授权
    Techniques for maintaining atomicity and ordering for pixel shader operations 有权

    公开(公告)号：US10055806B2

    公开(公告)日：2018-08-21

    申请号：US14924618

    申请日：2015-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

    Efficient super-sampling with per-pixel shader threads
    4.
    发明授权
    Efficient super-sampling with per-pixel shader threads 有权
    使用每像素着色器线程进行高效超采样

    公开(公告)号：US09495721B2

    公开(公告)日：2016-11-15

    申请号：US13725782

    申请日：2012-12-21

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. Duluk, Jr. ,  Rouslan Dimitrov ,  Eric Lum ,  Rui Bastos

    IPC: G06T1/20 ,  G06T15/00

    CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/005 ,  G06T2210/52

    Abstract: Techniques for dispatching pixel information in a graphics processing pipeline. A fragment processing unit generates a pixel that includes multiple samples based on a first portion of a graphics primitive received by a first thread. The fragment processing unit calculates a first value for the first pixel, where the first value is calculated only once for the pixel. The fragment processing unit calculates a first set of values for the samples, where each value in the first set of values corresponds to a different sample and is calculated only once for the corresponding sample. The fragment processing unit combines the first value with each value in the first set of values to create a second set of values. The fragment processing unit creates one or more dispatch messages to store the second set of values in a set of output registers.

    Abstract translation: 在图形处理流水线中调度像素信息的技术。 片段处理单元基于由第一线程接收的图形原语的第一部分生成包括多个样本的像素。 片段处理单元计算第一像素的第一值，其中第一值仅针对像素计算一次。 片段处理单元计算样本的第一组值，其中第一组值中的每个值对应于不同的样本，并且对于相应样本仅计算一次。 片段处理单元将第一值与第一组值中的每个值组合以创建第二组值。 片段处理单元创建一个或多个调度消息以将第二组值存储在一组输出寄存器中。

    Techniques for maintaining atomicity and ordering for pixel shader operations
    5.
    发明授权
    Techniques for maintaining atomicity and ordering for pixel shader operations 有权

    公开(公告)号：US10019776B2

    公开(公告)日：2018-07-10

    申请号：US14924624

    申请日：2015-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

    METHODS OF ELIMINATING REDUNDANT RENDERING OF FRAMES
    7.
    发明申请
    METHODS OF ELIMINATING REDUNDANT RENDERING OF FRAMES 审中-公开
    消除框架冗余渲染的方法

    公开(公告)号：US20150242988A1

    公开(公告)日：2015-08-27

    申请号：US14627496

    申请日：2015-02-20

    Applicant: Nvidia Corporation

    Inventor： Jeffrey Bolz ,  Xinheng Li ,  Eric Lum ,  Emmett Kilgariff

    IPC: G06T1/20 ,  G06T3/40 ,  G06T11/60

    CPC classification number: G06T1/20

    Abstract: A method for reducing redundant rendering of frames includes receiving draw calls including state information for a frame. The method includes generating respective bounding boxes for the draw calls. The bounding box is generated based on vertex data, vertex programs and transformation matrices. The method includes comparing the draw calls of the frame to the draw calls of one or more previous frames and identifying draw calls that are not identical in the compared frames. The method includes identifying the bounding boxes containing altered regions of the frames based on the draw calls that are not identical in the compared frames. The method includes reducing the altered regions into a smaller set of clip rectangles and rendering only inside the clip rectangles.

    Abstract translation: 用于减少帧的冗余渲染的方法包括接收包括帧的状态信息的绘制呼叫。 该方法包括为绘制调用生成相应的边界框。 边界框是基于顶点数据，顶点程序和变换矩阵生成的。 该方法包括将帧的绘制调用与一个或多个先前帧的绘制调用进行比较，并且识别在比较帧中不相同的绘制调用。 该方法包括基于在比较帧中不相同的绘制调用来识别包含帧的改变区域的边界框。 该方法包括将改变的区域减少为较小的一组剪辑矩形并且仅在剪辑矩形内部呈现。

    Techniques for maintaining atomicity and ordering for pixel shader operations
    10.
    发明申请
    Techniques for maintaining atomicity and ordering for pixel shader operations 审中-公开

    公开(公告)号：US20180374185A1

    公开(公告)日：2018-12-27

    申请号：US15999185

    申请日：2018-08-17

    Applicant: NVIDIA Corporation

    Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

    IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

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