公开(公告)号：US20140267376A1

公开(公告)日：2014-09-18

申请号：US13970542

申请日：2013-08-19

Applicant: NVIDIA Corporation

Inventor： Jeffrey Alan Bolz ,  Patrick R. Brown ,  Tyson Bergland ,  Alexander Lev Minkin

IPC: G06T5/00

CPC classification number: G06T1/60 ,  G06T5/002 ,  G06T11/40

Abstract: A system, method, and computer program product are provided for accessing multi-sample surfaces. A multi-sample store instruction that specifies data for a single sample of a multi-sample pixel and a sample mask is received and the data for the single sample is stored to each sample of the multi-sample pixel that is enabled according to the sample mask. A multi-sample load instruction that specifies a multi-sample pixel is received, and, in response to executing the multi-sample load instruction, data for one sample of the multi-sample pixel is received. A determination is made that the data for the one sample of the multi-sample pixel represents multi-sample pixel data for at least one additional sample of the multi-sample pixel.

Abstract translation: 提供了用于访问多样本表面的系统，方法和计算机程序产品。 接收多样本存储指令，指定多样本像素和样本掩模的单个样本的数据，并将单个样本的数据存储到根据样本启用的多样本像素的每个样本 面具。 接收指定多样本像素的多样本加载指令，并且响应于执行多样本加载指令，接收多样本像素的一个样本的数据。 确定多样本像素的一个样本的数据表示多样本像素的至少一个附加样本的多样本像素数据。

公开(公告)号：US10019776B2

公开(公告)日：2018-07-10

申请号：US14924624

申请日：2015-10-27

Applicant: NVIDIA CORPORATION

Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

公开(公告)号：US09754561B2

公开(公告)日：2017-09-05

申请号：US14046064

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Jonathan Dunaisky ,  Henry Packard Moreton ,  Jeffrey A. Bolz ,  Yury Y. Uralsky ,  James Leroy Deming ,  Rui M. Bastos ,  Patrick R. Brown ,  Amanpreet Grewal ,  Christian Amsinck ,  Poornachandra Rao ,  Jerome F. Duluk, Jr. ,  Andrew J. Tao

IPC: G06T1/60 ,  G06F12/08 ,  G06F12/10 ,  G09G5/39 ,  G06F12/0897 ,  G06F12/1027

CPC classification number: G09G5/39 ,  G06F12/0897 ,  G06F12/1027 ,  G06T1/60

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

公开(公告)号：US09665958B2

公开(公告)日：2017-05-30

申请号：US14010425

申请日：2013-08-26

Applicant: NVIDIA Corporation

Inventor： Jeffrey Alan Bolz ,  Patrick R. Brown ,  Tyson Bergland ,  Alexander Lev Minkin

IPC: G06T1/20 ,  G06T11/40 ,  G06F9/38 ,  G06T15/00

CPC classification number: G06T11/40 ,  G06F9/38 ,  G06T1/20 ,  G06T15/005

Abstract: A system, method, and computer program product are provided for redistributing multi-sample processing workloads between threads. A workload for a plurality of multi-sample pixels is received and each thread in a parallel thread group is associated with a corresponding multi-sample pixel of the plurality of pixels. The workload is redistributed between the threads in the parallel thread group based on a characteristic of the workload and the workload is processed by the parallel thread group. In one embodiment, the characteristic is rasterized coverage information for the plurality of multi-sample pixels.

公开(公告)号：US09448935B2

公开(公告)日：2016-09-20

申请号：US14037212

申请日：2013-09-25

Applicant: NVIDIA CORPORATION

Inventor： Jeff Bolz ,  Patrick R. Brown ,  Steven J. Heinrich ,  Dale L. Kirkland ,  Joel McCormack

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0815 ,  G06F12/1018 ,  G06F12/128 ,  G06F2212/455 ,  Y02D10/13

Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.

Abstract translation: 公开了用于执行存储器访问操作的技术。 纹理单元接收包括与多个视图中的第一视图相关联的元组的存储器访问操作。 纹理单元检索与多个纹理标题中的第一纹理标题相关联的第一散列值，其中第一纹理标题与第一视图相关。 纹理单元检索与多个纹理标题中的第二纹理标题相关联的第二散列值，其中第二纹理标题与第二视图相关。 基于第一和第二哈希值，纹理单元确定第一视图是否与第二视图潜在地别名。 如果是，则纹理单元使与第二纹理头相关联的高速缓冲存储器中的高速缓存条目无效。 否则，纹理单元维护高速缓存条目。

公开(公告)号：US09262797B2

公开(公告)日：2016-02-16

申请号：US13844095

申请日：2013-03-15

Applicant: NVIDIA Corporation

Inventor： Alexander Lev Minkin ,  Henry Packard Moreton ,  Yury Uralsky ,  Eric Brian Lum ,  Dale L. Kirkland ,  Steven James Heinrich ,  Rui Manuel Bastos ,  Emmett M. Kilgariff ,  Jeffrey Alan Bolz ,  Tyson Bergland ,  Patrick R. Brown

IPC: G06T1/60 ,  G06T5/00 ,  G06T11/40

CPC classification number: G06T1/60 ,  G06T5/002 ,  G06T11/40

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.

Abstract translation: 提供了一种用于多样本处理的系统，方法和计算机程序产品。 接收多采样像素数据，并确定与多样本像素数据相关联的编码状态。 将多样本像素的一个样本的数据和编码状态提供给处理单元。 多采样像素的一个样本由处理单元处理，以生成表示多采样像素的所有采样的多个样本像素的多个采样像素数据的一个样本的处理数据，或多样本像素的两个或多个样本 像素。

公开(公告)号：US10032245B2

公开(公告)日：2018-07-24

申请号：US14924628

申请日：2015-10-27

Applicant: NVIDIA CORPORATION

Inventor： Ziyad Hakura ,  Eric Lum ,  Dale Kirkland ,  Jack Choquette ,  Patrick R. Brown ,  Yury Y. Uralsky ,  Jeffrey Bolz

IPC: G06T1/20 ,  G06T1/60

Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

公开(公告)号：US20150054836A1

公开(公告)日：2015-02-26

申请号：US14010425

申请日：2013-08-26

Applicant: NVIDIA Corporation

Inventor： Jeffrey Alan Bolz ,  Patrick R. Brown ,  Tyson Bergland ,  Alexander Lev Minkin

IPC: G06T1/20

CPC classification number: G06T11/40 ,  G06F9/38 ,  G06T1/20 ,  G06T15/005

Abstract: A system, method, and computer program product are provided for redistributing multi-sample processing workloads between threads. A workload for a plurality of multi-sample pixels is received and each thread in a parallel thread group is associated with a corresponding multi-sample pixel of the plurality of pixels. The workload is redistributed between the threads in the parallel thread group based on a characteristic of the workload and the workload is processed by the parallel thread group. In one embodiment, the characteristic is rasterized coverage information for the plurality of multi-sample pixels.

Abstract translation: 提供了系统，方法和计算机程序产品，用于在线程之间重新分配多样本处理工作负载。 接收多个多样本像素的工作负载，并且并行线程组中的每个线程与多个像素中相应的多样本像素相关联。 基于工作负载的特性，并行线程组中的线程之间的工作量重新分配，并行线程组处理工作负载。 在一个实施例中，特征是用于多个多样本像素的光栅化覆盖信息。

公开(公告)号：US20140267356A1

公开(公告)日：2014-09-18

申请号：US13844147

申请日：2013-03-15

Applicant: NVIDIA CORPORATION

Inventor： Alexander Lev Minkin ,  Henry Packard Moreton ,  Yury Uralsky ,  Eric Brian Lum ,  Dale L. Kirkland ,  Steven James Heinrich ,  Rui Manuel Bastos ,  Emmett M. Kilgariff ,  Jeffrey Alan Bolz ,  Tyson Bergland ,  Patrick R. Brown

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T9/00 ,  G06T11/40

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets.

Abstract translation: 提供了一种用于多样本处理的系统，方法和计算机程序产品。 多样本像素数据被接收并被分析以识别具有相等数据的多采样像素的样本子集，使得子集中的一个样本的数据表示子集中所有样本的多样本像素数据。 生成编码状态，该编码状态指示多个样本像素的哪个样本被包括在每个子集中。

公开(公告)号：US20140267315A1

公开(公告)日：2014-09-18

申请号：US13844095

申请日：2013-03-15

Applicant: NVIDIA CORPORATION

Inventor： Alexander Lev Minkin ,  Henry Packard Moreton ,  Yury Uralsky ,  Eric Brian Lum ,  Dale L. Kirkland ,  Steven James Heinrich ,  Rui Manuel Bastos ,  Emmett M. Kilgariff ,  Jeffrey Alan Bolz ,  Tyson Bergland ,  Patrick R. Brown

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06T5/002 ,  G06T11/40

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.

Abstract translation: 提供了一种用于多样本处理的系统，方法和计算机程序产品。 接收多采样像素数据，并确定与多样本像素数据相关联的编码状态。 将多样本像素的一个样本的数据和编码状态提供给处理单元。 多采样像素的一个样本由处理单元处理，以生成表示多采样像素的所有采样的多个样本像素的多个采样像素数据的一个样本的处理数据，或多样本像素的两个或多个样本 像素。