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公开(公告)号：US11755524B2
公开(公告)日：2023-09-12
申请号：US17302752
申请日：2021-05-11
Applicant: NXP B.V.
Inventor： Matthias Berthold Muth
CPC classification number: G06F13/4072 , H03M5/145 , H03M5/20 , H03M13/33 , H04L2012/40215
Abstract: A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to:
detect rising edges in said bit stream;
detect, separately, falling edges in said bit stream; and
generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.-
公开(公告)号：US11516043B2
公开(公告)日：2022-11-29
申请号：US17248675
申请日：2021-02-02
Applicant: NXP B.V.
Inventor： Rainer Evers , Gerald Kwakernaat , Matthias Berthold Muth
Abstract: A transceiver has a first interface supplied by a first supply voltage to interface with external devices operating in a first supply domain and a second interface supplied by a second supply voltage and adapted to interface to an external communication bus operating in a second supply domain. The transceiver has a first internal communication link, which is adapted to transfer transmit data generated by an external device operating in the first supply domain, from the first interface to the second interface, and a second internal communication link, which is adapted to transfer transmit data be supplied from the external communication bus operating in the second supply domain from the second interface to the first interface.
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公开(公告)号：US20210377060A1
公开(公告)日：2021-12-02
申请号：US17302730
申请日：2021-05-11
Applicant: NXP B.V.
Inventor： Matthias Berthold Muth
Abstract: A Controller Area Network, CAN, transceiver comprising: two terminals for coupling to a CAN bus; a transmitter arrangement configured to transmit signalling on the bus based on transmit data, the transmitter arrangement configured to drive the bus to a dominant state or recessive state based on the transmit signal; an impedance control device; a signalling detector to determine the length of time the transmit data comprises a logic zero prior to a transition to a logic one state and: based on the length of time being longer than a predetermined threshold, provide for control of an output impedance by the impedance control device in accordance with a first scheme; and based on the length of time being shorter than said predetermined threshold, provide for one of: control of said output impedance in accordance with a second scheme; and no control of the output impedance by the impedance control device.
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公开(公告)号：US11190372B2
公开(公告)日：2021-11-30
申请号：US17248770
申请日：2021-02-05
Applicant: NXP B.V.
Abstract: A differential bus network comprising: a bus comprising two bus wires; at least three nodes each comprising: a transceiver comprising: bus terminals for coupling, respectively, to the two wires of the bus; a receiver arrangement configured to receive differential signalling from the bus terminals and determine a digital receive signal based on said differential signalling; and a transmitter arrangement configured to apply differential signalling to the bus terminals based on a digital transmit signal, the transmitter arrangement comprising a first transmitter configured to increase the potential difference between the wires of the bus to a first differential voltage state and maintain the first differential state and a suppression element configured to decrease the potential difference between the two wires of the bus towards a second differential voltage state, the transmitter arrangement further comprising a resistor coupled between the bus terminals configured to at least maintain the second differential voltage state.
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公开(公告)号：US20210258185A1
公开(公告)日：2021-08-19
申请号：US17248770
申请日：2021-02-05
Applicant: NXP B.V.
Abstract: A differential bus network comprising: a bus comprising two bus wires; at least three nodes each comprising: a transceiver comprising: bus terminals for coupling, respectively, to the two wires of the bus; a receiver arrangement configured to receive differential signalling from the bus terminals and determine a digital receive signal based on said differential signalling; and a transmitter arrangement configured to apply differential signalling to the bus terminals based on a digital transmit signal, the transmitter arrangement comprising a first transmitter configured to increase the potential difference between the wires of the bus to a first differential voltage state and maintain the first differential state and a suppression element configured to decrease the potential difference between the two wires of the bus towards a second differential voltage state, the transmitter arrangement further comprising a resistor coupled between the bus terminals configured to at least maintain the second differential voltage state.
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Patent Agency Ranking
公开(公告)号：US20210224079A1
公开(公告)日：2021-07-22
申请号：US17248224
申请日：2021-01-14
Applicant: NXP B.V.
Inventor： Matthias Berthold Muth
IPC: G06F9/4401 , H04L12/40 , H04L12/26 , H04B1/38
Abstract: The disclosure relates to a controller area network, CAN, transceiver and a CAN controller. The CAN transceiver is configured to: compare a signal from the CAN bus with a negative threshold level; and provide a wake-up indication to the CAN controller based on the signal matching a predetermined pattern of one or more periods in which the signal is less than the negative threshold level. The CAN controller is configured to provide instructions to transmit a wake-up indication on the CAN bus.
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公开(公告)号：US11038714B2
公开(公告)日：2021-06-15
申请号：US16885260
申请日：2020-05-27
Applicant: NXP B.V.
Inventor： Matthias Berthold Muth
IPC: H04L12/40 , H04L12/413
Abstract: A Controller Area Network, CAN, transceiver comprising a receiver arrangement for coupling to a CAN bus and configured to determine a differential signal from analog signalling received from the CAN bus; and a receive output for coupling to a CAN controller and wherein the receiver arrangement provides a digital output signal to the receive output based on the differential signal; wherein the receiver arrangement operates in at least a first mode in which it is configured to provide the digital output signal comprising logic 0 when the differential signal is greater than a first receiver threshold and provide the digital output signal comprising logic 1 when the differential signal is less than said first receiver threshold unless said differential signal satisfies a condition, whereupon the receiver arrangement is configured to provide the digital output signal comprising logic 0, wherein the condition comprises the differential signal being below an activity-voltage threshold.
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公开(公告)号：US11671280B2
公开(公告)日：2023-06-06
申请号：US17248769
申请日：2021-02-05
Applicant: NXP B.V.
Inventor： Bernd Uwe Gerhard Elend , Matthias Berthold Muth , Steffen Mueller
IPC: H04L12/40
CPC classification number: H04L12/40136 , H04L12/40006 , H04L12/40071 , H04L12/40078 , H04L12/40143 , H04L2012/40215
Abstract: A network node for coupling to a communication bus, the node comprising:
a receiver configured to receive messages from the communication bus; and a transmitter configured to transmit first messages having a first message format and configured to transmit diagnosis messages having a second message format on the communication bus for use in determination of communication errors, wherein said transmitter is configured to send said one or more diagnosis messages having one or more of:
(i) a predetermined pattern of symbols;
(ii) a predetermined sending schedule;
(iii) a predetermined line encoding method;
(iv) a predetermined bit rate;
(v) a predetermined position in one or more of the first messages;
(vi) a predetermined signalling frequency that is out of a frequency band used for transmission of the first messages; and
(vii) a predetermined signal strength different from the signal strength used to send the first messages.-
公开(公告)号：US20210250199A1
公开(公告)日：2021-08-12
申请号：US17248675
申请日：2021-02-02
Applicant: NXP B.V.
Inventor： Rainer Evers , Gerald Kwakernaat , Matthias Berthold Muth
Abstract: Disclosed are a transceiver device (100) and a method for interfacing between at least two different voltage domains (12, 14), namely a first supply voltage domain (12) having a higher first supply voltage and a second supply voltage domain (14) having a lower second supply voltage. The transceiver device (100) has: a first interface (110), which is supplied by the first supply voltage and is adapted to interface to at least one external first digital device (20) operating in the first supply voltage domain (12); a second interface (120), which is supplied by the second supply voltage and is adapted to interface to an external communication bus (24) operating in the second supply voltage domain (14); a first internal communication link (130), which is adapted to transfer transmit data, which can be generated by the external first digital device (20) operating in the first supply voltage domain (12), from the first interface (110) to the second interface (120), and a second internal communication link (170), which is adapted to transfer transmit data, which can be supplied from the external communication bus (24) operating in the second supply voltage domain (14), from the second interface (120) to the first interface (110). The transceiver device (100) may be embodied as a monolithic integrated circuit, which may be implemented in silicon-on-insulator, SOT, technology. The first and the second internal communication link (130, 170) may be based on the principles of one of differential voltage transmission (140, 180) and digital current loop transmission (150, 190).
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20.发明授权公开(公告)号：US10826719B2
公开(公告)日：2020-11-03
申请号：US16205778
申请日：2018-11-30
Applicant: NXP B.V.
Inventor： Matthias Berthold Muth , Georg Olma
IPC: H04L12/40 , H04L12/413 , H04L29/06 , H04B3/46 , H04L12/26
Abstract: The present application relates to a node for conducting measurements and signal analyses on a bus supporting multi-master access of a plurality of nodes or a transceiver of the node. The transceiver is configured to detect bus signals and to convert the detected bus signals into a bit stream. A protocol engine is arranged to receive the bit stream. The protocol engine transitions between states, which are indicative of at least an exclusive access phase, during which only one of the plurality of nodes is allowed to assert signals on the bus. A detector is configured to assert an enable indication for a period of time on detecting that the protocol engine is in a state indicative of the exclusive access phase. A diagnosis module is configured to conduct measurements in response to the asserted enable indication.
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