公开(公告)号：US06890822B2

公开(公告)日：2005-05-10

申请号：US10367591

申请日：2003-02-13

申请人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Ong Boon Teong ,  Oh Choong Young ,  Ng Chun Leng ,  Joung Joon Ho

发明人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Ong Boon Teong ,  Oh Choong Young ,  Ng Chun Leng ,  Joung Joon Ho

IPC分类号： H01L21/8234

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.