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    Semiconductor device with dual gate oxides
    1.
    发明授权
    Semiconductor device with dual gate oxides 失效
    具有双栅极氧化物的半导体器件

    公开(公告)号：US07259071B2

    公开(公告)日：2007-08-21

    申请号：US10973852

    申请日：2004-10-25

    申请人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Chiew Sin Ping ,  Wan Gie Lee ,  Choong Shiau Chien ,  Zadig Lam ,  Hitomi Watanabe ,  Naoto Inoue

    发明人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Chiew Sin Ping ,  Wan Gie Lee ,  Choong Shiau Chien ,  Zadig Lam ,  Hitomi Watanabe ,  Naoto Inoue

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/823462 ,  H01L21/823481 ,  Y10S438/981

    摘要： A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.

    摘要翻译： 制造具有第一有源区和第二有源区的半导体器件的方法包括提供在衬底上限定第一有源区的第一和第二隔离结构。 第一有源区域使用第一工作电压，而第二有源区域使用不同于第一电压的第二工作电压。 形成覆盖第一和第二有源区的氮化物层。 形成覆盖氮化物层的氧化物层。 去除覆盖在第一有源区上的氧化物层的第一部分以露出氮化物层的第一部分。 使用湿蚀刻方法去除氮化物层的暴露的第一部分，同时留下覆盖第二有源区域的氮化物层的第二部分完好无损。 此后，在第一有源区上形成具有第一厚度的第一栅极氧化物，第一栅极氧化物具有面对第一隔离结构的第一边缘和面向第二隔离结构的第二边缘。 第一边缘与第一隔离结构隔开第一距离。 第二边缘与第二隔离结构隔开第二距离。 此后，在第二有源区上形成具有第二厚度的第二栅极氧化物，第二厚度不同于第一厚度。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07166901B2

    公开(公告)日：2007-01-23

    申请号：US10950828

    申请日：2004-09-27

    申请人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Yeon Kim ,  In Ki Kim

    发明人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Yeon Kim ,  In Ki Kim

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0921 ,  H01L21/76237 ,  H01L21/823814 ,  H01L21/823878

    摘要： A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high voltage region of the semiconductor substrate, and low voltage MOS transistors disposed on the low voltage region of the semiconductor substrate. A first element isolator comprises a first shallow trench disposed on a surface of the low voltage, region of the semiconductor substrate, and a first dielectric embedded in the first shallow trench. A pair of second element isolators comprises two second shallow trenches spaced apart at an interval between a source region or a drain region of the pair of the adjacent high voltage MOS transistors and a source or a drain region of the other of the pair of the adjacent high voltage MOS transistors, and a second dielectric embedded in each of the second shallow trenches. The second shallow trenches are disposed on a surface of the high voltage region of the semiconductor substrate. A channel cut region having a high impurity concentration is disposed on the surface of the substrate between the second shallow trenches.

    摘要翻译： 半导体器件包括具有高电压区域和低电压区域的半导体衬底，设置在半导体衬底的高电压区域上的至少一对相邻的高压MOS晶体管和设置在低电压区域上的低压MOS晶体管 的半导体衬底。 第一元件隔离器包括设置在半导体衬底的低电压区域的表面上的第一浅沟槽和嵌入在第一浅沟槽中的第一电介质。 一对第二元件隔离器包括在一对相邻高压MOS晶体管的源极区域或漏极区域之间间隔开的两个第二浅沟槽和一对相邻的高压MOS晶体管中的另一个的源极或漏极区域 高电压MOS晶体管和嵌入在每个第二浅沟槽中的第二电介质。 第二浅沟槽设置在半导体衬底的高压区域的表面上。 具有高杂质浓度的沟道切割区域设置在第二浅沟槽之间的衬底表面上。

    Semiconductor device
    5.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050116265A1

    公开(公告)日：2005-06-02

    申请号：US10950828

    申请日：2004-09-27

    申请人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Kim ,  In Kim

    发明人： Naoto Inoue ,  Hitomi Sakurai ,  Min Paek ,  Sang Kim ,  In Kim

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/76

    CPC分类号： H01L27/0921 ,  H01L21/76237 ,  H01L21/823814 ,  H01L21/823878

    摘要： In a semiconductor device in which high voltage MOS transistors and low voltage MOS transistors are mixedly mounted, a process is simplified and miniaturization thereof is achieved, without causing a parasitic transistor operation. An active region doped with a low impurity concentration of an impurity is formed in a channel region of a parasitic MOS transistor between two STI (shallow trench isolation) regions, and current flow between a source and a drain of the parasitic MOS transistor is cut off in a semiconductor device in which a high voltage MOS transistor and a microscopic low voltage MOS transistor are mixedly mounted on the same semiconductor substrate.

    摘要翻译： 在混合安装高压MOS晶体管和低压MOS晶体管的半导体器件中，简化了工艺并实现了其小型化，而不会引起寄生晶体管的操作。 在两个STI（浅沟槽隔离）区域之间的寄生MOS晶体管的沟道区域中形成掺杂有杂质浓度低的有源区，并且将寄生MOS晶体管的源极与漏极之间的电流切断 在其中将高电压MOS晶体管和微观低电压MOS晶体管混合安装在同一半导体衬底上的半导体器件中。

    Semiconductor device having multiple gate oxide layers and method of manufacturing thereof
    6.
    发明授权
    Semiconductor device having multiple gate oxide layers and method of manufacturing thereof 失效
    具有多个栅极氧化物层的半导体器件及其制造方法

    公开(公告)号：US07208378B2

    公开(公告)日：2007-04-24

    申请号：US11126944

    申请日：2005-05-10

    申请人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Ong Boon Teong ,  Oh Choong Young ,  Ng Chun Leng ,  Joung Joon Ho

    发明人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Ong Boon Teong ,  Oh Choong Young ,  Ng Chun Leng ,  Joung Joon Ho

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823462 ,  Y10S438/981

    摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.

    摘要翻译： 制造半导体器件的方法包括在衬底上限定第一电压区域，第二电压区域和第三电压区域。 第一，第二和第三电压区域被配置为分别处理彼此不同的第一，第二和第三电压电平。 形成覆盖第一，第二和第三电压区域的氮化物层。 形成覆盖氮化物层的氧化物层。 图案化氧化物层以暴露覆盖第一电压区域的氮化物层的一部分。 使用湿蚀刻工艺去除氮化物层的暴露部分。 形成覆盖第一电压区域的第一栅极氧化物层。 除去覆盖第二和第三电压区域的氧化物层和氮化物层的部分。 杂质被选择性地注入到第三电压区域中，同时防止在第二电压区域中提供杂质。 覆盖第二电压区域的第二栅极氧化物和覆盖第三电压区域的第三栅极氧化物同时形成。 第二栅极氧化物比第三栅极氧化物厚。

    Semiconductor device with dual gate oxides
    7.
    发明授权
    Semiconductor device with dual gate oxides 有权
    具有双栅极氧化物的半导体器件

    公开(公告)号：US06818514B2

    公开(公告)日：2004-11-16

    申请号：US10377167

    申请日：2003-02-26

    申请人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Chiew Sin Ping ,  Wan Gie Lee ,  Choong Shiau Chien ,  Zadig Lam ,  Hitomi Watanabe ,  Naoto Inoue

    发明人： Inki Kim ,  Sang Yeon Kim ,  Min Paek ,  Chiew Sin Ping ,  Wan Gie Lee ,  Choong Shiau Chien ,  Zadig Lam ,  Hitomi Watanabe ,  Naoto Inoue

    IPC分类号： H01L218234

    CPC分类号： H01L21/823462 ,  H01L21/823481 ,  Y10S438/981

    摘要： A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.

    摘要翻译： 制造具有第一有源区和第二有源区的半导体器件的方法包括提供在衬底上限定第一有源区的第一和第二隔离结构。 第一有源区域使用第一工作电压，而第二有源区域使用不同于第一电压的第二工作电压。 形成覆盖第一和第二有源区的氮化物层。 形成覆盖氮化物层的氧化物层。 去除覆盖在第一有源区上的氧化物层的第一部分以露出氮化物层的第一部分。 使用湿蚀刻方法去除氮化物层的暴露的第一部分，同时留下覆盖第二有源区域的氮化物层的第二部分完好无损。 此后，在第一有源区上形成具有第一厚度的第一栅极氧化物，第一栅极氧化物具有面对第一隔离结构的第一边缘和面向第二隔离结构的第二边缘。 第一边缘与第一隔离结构隔开第一距离。 第二边缘与第二隔离结构隔开第二距离。 此后，在第二有源区上形成具有第二厚度的第二栅极氧化物，第二厚度不同于第一厚度。

    Semiconductor device having multiple gate oxide layers and method of manufacturing thereof
    10.
    发明申请
    Semiconductor device having multiple gate oxide layers and method of manufacturing thereof 失效
    具有多个栅极氧化物层的半导体器件及其制造方法

    公开(公告)号：US20050287745A1

    公开(公告)日：2005-12-29

    申请号：US11126944

    申请日：2005-05-10

    申请人： Inki Kim ,  Sang Kim ,  Min Paek ,  Ong Teong ,  Oh Young ,  Ng Leng ,  Joung Ho

    发明人： Inki Kim ,  Sang Kim ,  Min Paek ,  Ong Teong ,  Oh Young ,  Ng Leng ,  Joung Ho

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L21/823462 ,  Y10S438/981

    摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.

    摘要翻译： 制造半导体器件的方法包括在衬底上限定第一电压区域，第二电压区域和第三电压区域。 第一，第二和第三电压区域被配置为分别处理彼此不同的第一，第二和第三电压电平。 形成覆盖第一，第二和第三电压区域的氮化物层。 形成覆盖氮化物层的氧化物层。 图案化氧化物层以暴露覆盖第一电压区域的氮化物层的一部分。 使用湿蚀刻工艺去除氮化物层的暴露部分。 形成覆盖第一电压区域的第一栅极氧化物层。 除去覆盖第二和第三电压区域的氧化物层和氮化物层的部分。 杂质被选择性地注入到第三电压区域中，同时防止在第二电压区域中提供杂质。 覆盖第二电压区域的第二栅极氧化物和覆盖第三电压区域的第三栅极氧化物同时形成。 第二栅极氧化物比第三栅极氧化物厚。