公开(公告)号：US06829715B2

公开(公告)日：2004-12-07

申请号：US09865844

申请日：2001-05-25

申请人： Jennifer Y. Chiao ,  Gary A. Alvstad ,  Myles H. Wakayama

发明人： Jennifer Y. Chiao ,  Gary A. Alvstad ,  Myles H. Wakayama

IPC分类号： G06F104

CPC分类号： G06F1/10 ,  G06F2213/0024

摘要： A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.

摘要翻译： 具有与同步器反馈延迟环耦合的预测同步器和复制延迟元件的预测时基发生器。 预测时基发生器接收延迟了预定时钟延迟的时钟信号，并产生一个预测时间信号，该预测时间信号在时间上提前由复制延迟元件表示的量。 复制延迟元件可以复制预定时钟延迟和预定数据延迟中的一个或两个，从而基本上使设备的关键信号路径中的相应延迟无效。 复制延迟元件可以包括在输入时钟路径和输出数据路径中找到的结构的副本，这些元件包括例如电压电平移位器，缓冲器或数据锁存器，多路复用器，线元模型等。 还提供了一种包含上述预测时基发生器的预测计算机总线接口适配器。 这种预测接口适配器可以适应于遵守在PCI和PCI-X局部总线协议下施加的严格总线协议时序预算，并且相对于设计和制造过程以及环境操作条件的变化而言是稳健的。

公开(公告)号：US06181210B2

公开(公告)日：2001-01-30

申请号：US09398101

申请日：1999-09-16

申请人： Myles H. Wakayama

发明人： Myles H. Wakayama

IPC分类号： H03L7093

CPC分类号： H03L7/0898 ,  H03L7/0896

摘要： A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

摘要翻译： 设计并构造了一个结合了相位/频率检测器的锁相环中使用的高精度电荷泵，从而大大消除了电荷泵输出电流下的直流偏移和毛刺误差的影响。 高精度电荷泵由平行电流路径构成，每个电路具有中心节点，中心节点又连接到反馈元件。 反馈元件定义了一个反馈电流，该电流被施加到电荷泵上，以便将两个中心节点保持在等电位电平，并且将降压电流的值保持正确地等于泵浦电流的值 由设备输出。

公开(公告)号：US5079518A

公开(公告)日：1992-01-07

申请号：US614203

申请日：1990-11-16

申请人： Myles H. Wakayama

发明人： Myles H. Wakayama

IPC分类号： H03F3/343 ,  H03F3/345

CPC分类号： H03F3/345

摘要： A current-mirror circuit includes a pair of NMOS transistors. The first NMOS transistor has a gate electrode, a drain electrode serving as a current input terminal of the current-mirror circuit and a source electrode connected to a preselected potential. The second NMOS transistor has a gate electrode connected to the gate electrode of the first NMOS transistor, a drain electrode serving as a current output terminal of the current-mirror circuit and a source electrode connected to the preselected potential. The current-mirror circuit is provided with a buffer circuit. The buffer circuit includes a bipolar transistor which is opposite in polarity to the paired NMOS transistors, i.e., a PNP bipolar transistor. This transistor is associated with a constant current source.