公开(公告)号：US20190222216A1

公开(公告)日：2019-07-18

申请号：US16248951

申请日：2019-01-16

申请人： Analog Bits Inc.

发明人： Alan C. Rogers ,  Raghunand Bhagwan

IPC分类号： H03L7/089

CPC分类号： H03L7/0891 ,  H03L7/0896

摘要： A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

公开(公告)号：US09991896B2

公开(公告)日：2018-06-05

申请号：US15668392

申请日：2017-08-03

申请人： Synopsys, Inc.

发明人： Amit Katyal

IPC分类号： H03L7/06 ,  H03L7/089 ,  H03L7/107 ,  H03L7/097 ,  H03L7/099

CPC分类号： H03L7/0891 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/097 ,  H03L7/099 ,  H03L7/1072

摘要： A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.

公开(公告)号：US20180145695A1

公开(公告)日：2018-05-24

申请号：US15356335

申请日：2016-11-18

申请人： STMicroelectronics International N.V.

发明人： Abhirup Lahiri ,  Nitin Gupta ,  Gagan Midha

IPC分类号： H03L7/093 ,  H02M3/07 ,  H03L7/08 ,  H03L7/099

CPC分类号： H03L7/093 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0991 ,  H03L7/1976

摘要： An embodiment circuit includes a first charge pump configured to generate a first current at a first node, and a second charge pump configured to generate a second current at a second node. The circuit further includes an isolation buffer coupled between the first node and the second node and an adder having a first input coupled to the second node. The circuit additionally includes an auxiliary charge pump configured to generate a third current at a second input of the adder, and an oscillator having an input coupled to an output of the adder.

公开(公告)号：US20180048322A1

公开(公告)日：2018-02-15

申请号：US15668392

申请日：2017-08-03

申请人： Synopsys, Inc.

发明人： Amit Katyal

IPC分类号： H03L7/089 ,  H03L7/097 ,  H03L7/099 ,  H03L7/107

CPC分类号： H03L7/0891 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/097 ,  H03L7/099 ,  H03L7/1072

摘要： A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.

公开(公告)号：US09871527B2

公开(公告)日：2018-01-16

申请号：US15419587

申请日：2017-01-30

申请人： International Business Machines Corporation

发明人： David M. Friend ,  Grant P. Kesselring ,  Michael A. Sperling ,  James D. Strom

IPC分类号： H03L7/093 ,  H03L7/099 ,  H02M3/07 ,  H03F3/45

CPC分类号： H03K5/02 ,  H02M3/07 ,  H03F3/45179 ,  H03F2203/45116 ,  H03L7/0896 ,  H03L7/093 ,  H03L7/099

摘要： A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.

公开(公告)号：US20180013436A1

公开(公告)日：2018-01-11

申请号：US15410890

申请日：2017-01-20

申请人： NXP USA, Inc.

发明人： Pierre Pascal Savary ,  Dominique Delbecq ,  Birama Goumballa

IPC分类号： H03L7/089

CPC分类号： H03L7/0896 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/183

摘要： A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.

公开(公告)号：US20170358329A1

公开(公告)日：2017-12-14

申请号：US15616125

申请日：2017-06-07

申请人： NXP USA, Inc.

发明人： Birama Goumballa ,  Cristian Pavao Moreira ,  Pierre Pascal Savary

IPC分类号： G11C5/14 ,  G05F1/10 ,  H03K3/03 ,  H02M3/07 ,  H02M1/00

CPC分类号： G11C5/145 ,  G05F1/10 ,  H02M3/07 ,  H02M2001/0003 ,  H03K3/03 ,  H03L7/0895 ,  H03L7/0896

摘要： A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.

公开(公告)号：US09413363B2

公开(公告)日：2016-08-09

申请号：US14451966

申请日：2014-08-05

申请人： SanDisk Technologies Inc.

发明人： Simon Bass ,  Alexander Tetelbaum

IPC分类号： H03L7/089 ,  H02M3/07

CPC分类号： H03L7/0891 ,  H02M3/07 ,  H03L7/0895 ,  H03L7/0896

摘要： A charge pump provides matched charging and discharging currents. One transistor is connected to an input of a charge pump core while two transistors are connected to the other input of the charge pump core, with each of the transistors mirroring a reference transistor through different mirroring pathways so that current through the transistor of the first input is equal to the sum of currents through the two transistors of the second input.

摘要翻译： 电荷泵提供匹配的充电和放电电流。 一个晶体管连接到电荷泵芯的输入端，而两个晶体管连接到电荷泵芯的另一个输入，晶体管中的每一个通过不同的镜像通路镜像参考晶体管，使得通过第一输入晶体管 等于通过第二输入的两个晶体管的电流之和。

公开(公告)号：US09401722B2

公开(公告)日：2016-07-26

申请号：US13525285

申请日：2012-06-16

申请人： Ajay kumar ,  Krishnaswamy Nagaraj ,  Joonsung Park

发明人： Ajay kumar ,  Krishnaswamy Nagaraj ,  Joonsung Park

IPC分类号： H03L7/099 ,  H03L7/02 ,  H03L7/093 ,  H03L7/089 ,  H03L7/107 ,  H03L7/06 ,  H03L7/18

CPC分类号： H03L7/107 ,  H03L7/06 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/1072 ,  H03L7/1075 ,  H03L7/18 ,  H03L2207/04

摘要： A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.

摘要翻译： 锁相环（PLL）包括被编程为自动产生一组控制信号以选择电荷泵电流并且积分电容值以自动调整PLL的环路带宽的状态机。 电荷泵DAC产生由状态机控制信号控制的电荷泵电流。 积分器集成了电荷泵输出电流，以产生集成的电荷泵输出信号。 积分器具有通过来自状态机的控制信号可切换地选择的多个电容器，以产生积分电容值。 压控振荡器（VCO）响应于集成的电荷泵输出信号产生PLL输出频率。

公开(公告)号：US09369265B1

公开(公告)日：2016-06-14

申请号：US14882784

申请日：2015-10-14

申请人： SK hynix Inc. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Gi-Moon Hong ,  Suhwan Kim ,  Deog-Kyoon Jeong

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H03L7/089 ,  H03L7/087 ,  H04L7/04

CPC分类号： H04L7/0079 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0896 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0037 ,  H04L7/02 ,  H04L7/0337 ,  H04L7/04

摘要： A data receiver includes a sampling clock generator configured to generate a sampling clock signal from an internal clock signal according to a data strobe signal, and a sampler configured to sample a data signal according to the sampling clock signal.

摘要翻译： 数据接收机包括：采样时钟发生器，被配置为根据数据选通信号从内部时钟信号产生采样时钟信号;以及采样器，被配置为根据采样时钟信号对数据信号进行采样。