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公开(公告)号：US07366940B2
公开(公告)日：2008-04-29
申请号：US10990657
申请日：2004-11-17
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F2213/0024
摘要： A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.
摘要翻译： 具有与同步器反馈延迟环耦合的预测同步器和复制延迟元件的预测时基发生器。 预测时基发生器接收延迟了预定时钟延迟的时钟信号，并产生一个预测时间信号，该预测时间信号在时间上提前由复制延迟元件表示的量。 复制延迟元件可以复制预定时钟延迟和预定数据延迟中的一个或两个，从而基本上使设备的关键信号路径中的相应延迟无效。 复制延迟元件可以包括在输入时钟路径和输出数据路径中找到的结构的副本，这些元件包括例如电压电平移位器，缓冲器或数据锁存器，多路复用器，线元模型等。 还提供了一种包含上述预测时基发生器的预测计算机总线接口适配器。 这种预测接口适配器可以适应于遵守在PCI和PCI-X局部总线协议下施加的严格总线协议时序预算，并且相对于设计和制造过程以及环境操作条件的变化而言是稳健的。
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公开(公告)号：US5043943A
公开(公告)日：1991-08-27
申请号：US539651
申请日：1990-06-18
CPC分类号： G06F11/1064 , G06F12/0802
摘要： A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE.sub.x) signals to enable a write amplifier to individually write a single parity bit to a selected memory location. The SRAM is designed to function in either a parity or a non-parity mode. A bonding option pad is connected to parity control logic circuitry, and determines whether the SRAM will function in the parity mode or the non-parity mode. The parity control logic circuitry generates a parity signal, based on the electrical connection of the option pad. Thus, when the option pad is connected to ground, the parity option is selected, whereas, when the option pad is connected to a positive power supply, then non-parity functionality is selected. When parity functionality is selected, the the SRAM will allow the four (4) independent BWE.sub.x signals to individually enable the write amplifier. When non-parity functionality is selected, a single control signal will enable the write amplifier, and the SRAM functions as a standard memory device.
摘要翻译： 提供了具有支持字节奇偶校验能力的奇偶校验SRAM。 奇偶校验SRAM使用四（4）个独立字节写使能（BWEx）信号，使写放大器可以将单个奇偶校验位单独写入所选存储单元。 SRAM被设计为以奇偶校验或非奇偶校验方式工作。 键合选项焊盘连接到奇偶校验控制逻辑电路，并确定SRAM是否将在奇偶校验模式或非奇偶校验模式下工作。 奇偶校验控制逻辑电路基于选件板的电连接产生奇偶校验信号。 因此，当选件焊盘连接到地时，选择奇偶选项，而当选件焊盘连接到正电源时，则选择非奇偶校验功能。 当选择奇偶校验功能时，SRAM将允许四（4）个独立BWEx信号单独启用写放大器。 当选择非奇偶校验功能时，单个控制信号将使能写入放大器，并且SRAM用作标准存储器件。
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公开(公告)号：US06829715B2
公开(公告)日：2004-12-07
申请号：US09865844
申请日：2001-05-25
IPC分类号： G06F104
CPC分类号： G06F1/10 , G06F2213/0024
摘要： A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.
摘要翻译： 具有与同步器反馈延迟环耦合的预测同步器和复制延迟元件的预测时基发生器。 预测时基发生器接收延迟了预定时钟延迟的时钟信号，并产生一个预测时间信号，该预测时间信号在时间上提前由复制延迟元件表示的量。 复制延迟元件可以复制预定时钟延迟和预定数据延迟中的一个或两个，从而基本上使设备的关键信号路径中的相应延迟无效。 复制延迟元件可以包括在输入时钟路径和输出数据路径中找到的结构的副本，这些元件包括例如电压电平移位器，缓冲器或数据锁存器，多路复用器，线元模型等。 还提供了一种包含上述预测时基发生器的预测计算机总线接口适配器。 这种预测接口适配器可以适应于遵守在PCI和PCI-X局部总线协议下施加的严格总线协议时序预算，并且相对于设计和制造过程以及环境操作条件的变化而言是稳健的。
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公开(公告)号：US5291455A
公开(公告)日：1994-03-01
申请号：US880381
申请日：1992-05-08
申请人： Taisheng Feng , John D. Porter , Jennifer Y. Chiao
发明人： Taisheng Feng , John D. Porter , Jennifer Y. Chiao
IPC分类号： G11C11/417 , G11C5/14 , G11C11/401 , G11C11/407 , H01L27/10 , H03K19/00
摘要： A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.
摘要翻译： 存储器（20）具有在靠近放大器（84和85）和地址缓冲器（76）的点处耦合到正和负电源线（61和62）的NBIAS发生器（63和73），以确保它们都接收 相同的电源电压以防止对存储器（20）的访问时间的影响。 VCS发生器（65）位于电源接合焊盘（23和25）附近以及输出缓冲器（77和78），以减少电源线噪声对噪声容限的影响。 VAREF发生器向地址缓冲器（75和76）的差分放大器提供参考电压。 将VAREF发生器（67）放置在电源接合焊盘（23和25）附近，确保参考电压始终处于输入逻辑摆幅的中点。
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公开(公告)号：US5293081A
公开(公告)日：1994-03-08
申请号：US951620
申请日：1992-09-28
CPC分类号： G06F7/53 , G06F7/57 , G06F7/49905
摘要： A driver circuit (33) for output buffers or the like provides differing switching speed and di/dt depending on whether an output signal is switched in response to input signals or a control signal.
摘要翻译： 用于输出缓冲器等的驱动电路（33）根据输入信号或控制信号是否切换输出信号，提供不同的切换速度和di / dt。
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公开(公告)号：US5184033A
公开(公告)日：1993-02-02
申请号：US763018
申请日：1991-09-20
IPC分类号： H01L27/06 , H01L21/8249 , H03K5/08 , H03K17/16 , H03K17/567 , H03K19/003 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/017527 , H03K19/00346 , H03K19/017518
摘要： A regulated BiCMOS output buffer (34) regulates a logic high voltage of an output signal to improve interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.
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