公开(公告)号：US11476390B2

公开(公告)日：2022-10-18

申请号：US17161571

申请日：2021-01-28

Applicant: Ostendo Technologies, Inc.

Inventor： Hussein S. El-Ghoroury ,  Qian Fan ,  Kameshwar Yadavalli

IPC: H01L33/30 ,  H01L27/15 ,  H01L33/62

Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.

公开(公告)号：US09978582B2

公开(公告)日：2018-05-22

申请号：US15379759

申请日：2016-12-15

Applicant: Ostendo Technologies, Inc.

Inventor： Gregory Batinica ,  Kameshwar Yadavalli ,  Qian Fan ,  Benjamin A. Haskell ,  Hussein S. El-Ghoroury

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L29/30

CPC classification number: H01L21/02035 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02172 ,  H01L21/02274 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/94 ,  H01L29/2003 ,  H01L29/30 ,  H01L2224/94 ,  H01L2924/3511

Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.