公开(公告)号：US20220103773A1

公开(公告)日：2022-03-31

申请号：US17549035

申请日：2021-12-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinichi MACHIDA ,  Takeyoshi TOKUHARA ,  Manabu NAKATA ,  Sanshiro SHISHIDO ,  Masaaki YANAGIDA ,  Masumi IZUCHI

IPC: H04N5/378 ,  H01L27/30 ,  H04N5/374 ,  H01L51/42

Abstract: An imaging apparatus includes a unit pixel including a pixel electrode, a charge accumulation region electrically connected to the pixel electrode, and a signal detection circuit electrically connected to the charge accumulation region; a counter electrode facing the pixel electrode; a photoelectric conversion layer disposed between the electrodes; and a voltage supply circuit configured to selectively apply any one of first, second, and third voltages between the electrodes. The photoelectric conversion layer exhibits first and second wavelength sensitivity characteristics in a wavelength range when the voltage supply circuit applies the first and second voltages between the electrodes, respectively, and becomes insensitive to light in the wavelength range when the voltage supply circuit applies the third voltage between the electrodes.

公开(公告)号：US20210366960A1

公开(公告)日：2021-11-25

申请号：US17391793

申请日：2021-08-02

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yuuko TOMEKAWA ,  Takahiro KOYANAGI ,  Takeyoshi TOKUHARA

IPC: H01L27/146 ,  H01L49/02

Abstract: A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer has a thickness of 10 nm or more. The first electrode contains carbon. At the interface between the dielectric layer and the first electrode, an elemental percentage of carbon is 30 atomic % or less.

公开(公告)号：US20210195122A1

公开(公告)日：2021-06-24

申请号：US17173031

申请日：2021-02-10

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Shinichi MACHIDA ,  Masashi MURAKAMI ,  Takeyoshi TOKUHARA ,  Masaaki YANAGIDA ,  Sanshiro SHISHIDO ,  Manabu NAKATA ,  Masumi IZUCHI

IPC: H04N5/33 ,  H01L27/30 ,  H04N5/378 ,  H04N9/04 ,  H04N5/374

Abstract: An imaging apparatus includes a unit pixel including a pixel electrode; a counter electrode facing the pixel electrode; a photoelectric conversion layer disposed between the pixel electrode and the counter electrode; and a computing circuit that acquires a first signal upon a first voltage being applied between the pixel electrode and the counter electrode, the first signal corresponding to an image captured with visible light and infrared light and a second signal upon a second voltage being applied between the pixel electrode and the counter electrode, the second signal corresponding to an image captured with visible light, and generates a third signal by performing a computation using the first signal and the second signal, the third signal corresponding to an image captured with infrared light.

公开(公告)号：US20210043688A1

公开(公告)日：2021-02-11

申请号：US17078440

申请日：2020-10-23

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Shunsuke ISONO ,  Hidenari KANEHARA ,  Sanshiro SHISHIDO ,  Takeyoshi TOKUHARA

IPC: H01L27/30 ,  H04N5/374 ,  H04N5/376 ,  H01L27/146

Abstract: An imaging device including a semiconductor substrate including a pixel region and a peripheral region; an insulating layer covering the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer covering the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry electrically connected to the first electrodes; peripheral circuitry electrically connected to the detection circuitry, and; and a third electrode located on the insulating layer. The second electrode includes a connection region in which the second electrode is connected to third electrode, the connection region overlaps analog circuitry in a plan view, and in any cross-sections perpendicular to a surface of the semiconductor substrate and parallel to a column or row direction and that intersects at least one of the first electrodes, the digital circuitry includes no transistor that is located directly below the connection region.