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公开(公告)号：US20210366992A1
公开(公告)日：2021-11-25
申请号：US17394091
申请日：2021-08-04
Inventor： Shunsuke ISONO , Hidenari KANEHARA , Sanshiro SHISHIDO , Takeyoshi TOKUHARA
IPC: H01L27/30 , H04N5/374 , H04N5/376 , H01L27/146
Abstract: An imaging device including: a semiconductor substrate including a pixel region and a peripheral region; an insulating layer that covers the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer that covers the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry configured to be electrically connected to the first electrodes; peripheral circuitry configured to be electrically connected to the detection circuitry, and including analog circuitry; and a third electrode electrically connected to the second electrode. The third electrode overlaps the analog circuitry in a plan view, and in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the third electrode, no transistor of the digital circuitry is located directly below the third electrode.
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公开(公告)号：US20210013252A1
公开(公告)日：2021-01-14
申请号：US17039018
申请日：2020-09-30
Inventor： Kyosuke KOBINATA , Sanshiro SHISHIDO , Yoshihiro SATO
IPC: H01L27/146 , H01L31/0224
Abstract: An imaging device including a semiconductor substrate; a first pixel including a first photoelectric converter configured to convert incident light into charge, and a first diffusion region in the semiconductor substrate, configured to electrically connected to the first photoelectric converter and a second pixel including a second photoelectric converter, configured to convert incident light into charge, and a second diffusion region in the semiconductor substrate, configured to electrically connected to the second photoelectric converter, wherein an area of the first photoelectric converter is greater than an area of the second photoelectric converter in a plan view, both the first diffusion region and the second diffusion region overlap with the first photoelectric converter in the plan view, and neither the first diffusion region nor the second diffusion region overlaps with the second photoelectric converter in the plan view.
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公开(公告)号：US20250107312A1
公开(公告)日：2025-03-27
申请号：US18977399
申请日：2024-12-11
Inventor： Sanshiro SHISHIDO , Takahiro KOYANAGI , Yuuko TOMEKAWA , Shinichi MACHIDA
Abstract: An imaging device includes a first pixel and a second pixel adjacent to the first pixel. Each of the first pixel and the second pixel includes a first electrode, a second electrode positioned on or above the first electrode and facing the first electrode, a photoelectric conversion layer positioned between the first electrode and the second electrode, and a first charge-blocking layer positioned between the first electrode and the photoelectric conversion layer. The first charge-blocking layer of the first pixel is separated from the first charge-blocking layer of the second pixel. The photoelectric conversion layer is disposed continuously to the first pixel and the second pixel. An area of the first charge-blocking layer of the first pixel is larger than an area of the first electrode of the first pixel in plan view.
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公开(公告)号：US20240313012A1
公开(公告)日：2024-09-19
申请号：US18671434
申请日：2024-05-22
Inventor： Sanshiro SHISHIDO , Masashi MURAKAMI , Kazuko NISHIMURA
IPC: H01L27/146 , H04N23/50 , H04N23/55 , H04N25/57 , H04N25/585 , H04N25/75 , H04N25/76
CPC classification number: H01L27/14612 , H01L27/14609 , H01L27/14627 , H01L27/14643 , H04N25/57 , H04N25/585 , H04N25/75 , H04N25/76 , H04N23/50 , H04N23/55
Abstract: An imaging device including a semiconductor substrate; a first photoelectric converter that is located in the semiconductor substrate and that generates a first signal charge by photoelectric conversion; a first node to which the first signal charge is input; a capacitor having a first terminal coupled to the first node; and a second photoelectric converter that is located in the semiconductor substrate and that generates a second signal charge by photoelectric conversion. The area of the second photoelectric converter is greater than the area of the first photoelectric converter in a plan view, and the number of saturation charges of a first imaging cell including the first photoelectric converter and the capacitor is greater than the number of saturation charges of a second imaging cell including the second photoelectric converter.
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公开(公告)号：US20180331141A1
公开(公告)日：2018-11-15
申请号：US16045553
申请日：2018-07-25
Inventor： Sanshiro SHISHIDO , Masashi MURAKAMI , Kazuko NISHIMURA
IPC: H01L27/146 , H04N5/378 , H04N5/374 , H04N5/355
CPC classification number: H01L27/14612 , H01L27/14609 , H01L27/14627 , H01L27/14643 , H04N5/355 , H04N5/35563 , H04N5/374 , H04N5/378
Abstract: In one general aspect, the techniques disclosed here feature an imaging device that includes: a semiconductor substrate; a first pixel cell including a first photoelectric converter in the semiconductor substrate, and a first capacitive element one end of which is electrically connected to the first photoelectric converter; and a second pixel cell including a second photoelectric converter in the semiconductor substrate. An area of the second photoelectric converter is larger than an area of the first photoelectric converter in a plan view.
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Patent Agency Ranking
公开(公告)号：US20160142661A1
公开(公告)日：2016-05-19
申请号：US15003410
申请日：2016-01-21
Inventor： Sanshiro SHISHIDO , Masahiro HIGUCHI
CPC classification number: H04N5/3658 , H03M1/1245 , H04N5/357 , H04N5/3651 , H04N5/3698 , H04N5/3742 , H04N5/37455 , H04N5/378
Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.
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公开(公告)号：US20230262346A1
公开(公告)日：2023-08-17
申请号：US18303285
申请日：2023-04-19
Inventor： Tsutomu KOBAYASHI , Kazuko NISHIMURA , Yasuo MIYAKE , Sanshiro SHISHIDO
Abstract: A camera system includes: a photoelectric converter including a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, the photoelectric conversion layer converting incident light into electric charge; voltage application circuitry that supplies a first voltage and a second voltage less than the first voltage between the first electrode and the second electrode such that the first voltage is applied at least one time in a frame; and a controller that derives a total length of at least one period in which the first voltage is applied in the frame, the total length corresponding to an attenuation ratio set for the frame, and causes the voltage supply circuitry to supply the first voltage in the at least one period having the total length in the frame.
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公开(公告)号：US20230097274A1
公开(公告)日：2023-03-30
申请号：US18077127
申请日：2022-12-07
Inventor： Sanshiro SHISHIDO , Masashi MURAKAMI , Kazuko NISHIMURA
IPC: H01L27/146 , H04N5/355 , H04N5/374 , H04N5/378 , H04N5/225
Abstract: An imaging device that includes a semiconductor substrate; a first photoelectric converter that is located in the semiconductor substrate and that generates a first signal charge by photoelectric conversion; a first node to which the first signal charge is input; a capacitor having a first terminal coupled to the first node; a second photoelectric converter that is located in the semiconductor substrate and that generates a second signal charge by photoelectric conversion; a second node to which the second signal charge is input; a transistor having a gate coupled to the second node; and a switch element coupled between the first node and the second node, where a number of saturation charges of a first imaging cell including the first photoelectric converter and the capacitor is greater than a number of saturation charges of a second imaging cell including the second photoelectric converter.
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9.发明申请公开(公告)号：US20200036915A1
公开(公告)日：2020-01-30
申请号：US16595292
申请日：2019-10-07
Inventor： Shinichi MACHIDA , Masashi MURAKAMI , Takeyoshi TOKUHARA , Masaaki YANAGIDA , Sanshiro SHISHIDO , Manabu NAKATA , Masumi IZUCHI
Abstract: An imaging apparatus includes a unit pixel including a pixel electrode; a counter electrode facing the pixel electrode; a photoelectric conversion layer disposed between the pixel electrode and the counter electrode; and a computing circuit that acquires a first signal upon a first voltage being applied between the pixel electrode and the counter electrode, the first signal corresponding to an image captured with visible light and infrared light and a second signal upon a second voltage being applied between the pixel electrode and the counter electrode, the second signal corresponding to an image captured with visible light, and generates a third signal by performing a computation using the first signal and the second signal, the third signal corresponding to an image captured with infrared light.
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公开(公告)号：US20150077610A1
公开(公告)日：2015-03-19
申请号：US14554005
申请日：2014-11-25
Inventor： Sanshiro SHISHIDO , Masahiro HIGUCHI
IPC: H04N5/374 , H04N5/357 , H04N5/3745 , H04N5/378
CPC classification number: H04N5/3658 , H03M1/1245 , H04N5/357 , H04N5/3651 , H04N5/3698 , H04N5/3742 , H04N5/37455 , H04N5/378
Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.
Abstract translation: 固态成像装置包括产生用于A / D转换的参考电压的D / A转换电路。 D / A转换电路包括：电压产生电路，根据数字信号产生模拟电压; 缓冲电路，缓冲所产生的模拟电压的缓冲电路，缓冲电路采样并保持在缓冲电路内产生的偏置电压，并使用保持的偏置电压输出缓冲的模拟电压; 模拟信号输出单元（电阻梯形单元），通过接收来自缓冲电路的输出，根据输入的数字信号输出参考电压; 以及与缓冲电路的采样和保持相结合对降噪电容器充电的预充电放大器，降噪电容器连接到模拟信号输出单元。
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