公开(公告)号：US20110176244A1

公开(公告)日：2011-07-21

申请号：US12690771

申请日：2010-01-20

申请人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

发明人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

IPC分类号： H02H9/04 ,  H01L21/331 ,  H01L29/73

CPC分类号： H01L29/66234 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（＆Dgr; Vt1）MAX的最大值（例如，由半导体晶粒或晶片上的晶体管（21,21'，70,700）的不同方位取向） 大大减少。 触发电压一致性和制造产量提高。

公开(公告)号：US08982516B2

公开(公告)日：2015-03-17

申请号：US13750057

申请日：2013-01-25

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H02H9/00 ,  H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0262

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

摘要翻译： 提供一种区域高效，高电压，单极性的ESD保护装置（300），其包括p型衬底（303）; 第一p阱（308-1），其形成在所述衬底中并且尺寸设置成包含连接到阴极端子的n +和p +接触区域（310,312）; 形成在所述基板中并且尺寸仅包含连接到阳极端子的p +接触区域（311）的第二独立p阱（308-2） 以及形成在基板中以围绕和分离第一和第二半导体区域的电浮置n型隔离结构（304,306,307-2）。 当超过触发电压电平的正电压被施加到阴极和阳极端子时，ESD保护装置将固有的可控硅触发到快速恢复模式，以提供通过用于放电ESD电流的结构的低阻抗路径。

公开(公告)号：US20140211346A1

公开(公告)日：2014-07-31

申请号：US13750057

申请日：2013-01-25

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H02H9/04 ,  H01L21/02

CPC分类号： H02H9/046 ,  H01L27/0262

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

摘要翻译： 提供一种区域高效，高电压，单极性的ESD保护装置（300），其包括p型衬底（303）; 第一p阱（308-1），其形成在所述衬底中并且尺寸设置成包含连接到阴极端子的n +和p +接触区域（310,312）; 形成在所述基板中并且尺寸仅包含连接到阳极端子的p +接触区域（311）的第二独立p阱（308-2） 以及形成在基板中以围绕和分离第一和第二半导体区域的电浮置n型隔离结构（304,306,307-2）。 当超过触发电压电平的正电压被施加到阴极和阳极端子时，ESD保护装置将固有的可控硅触发到快速恢复模式，以提供通过用于放电ESD电流的结构的低阻抗路径。

公开(公告)号：US20130157433A1

公开(公告)日：2013-06-20

申请号：US13770548

申请日：2013-02-19

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L29/66

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1

摘要翻译： 提供了形成静电放电保护（ESD）夹具的方法。 在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。 至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。 晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。 第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。 选择第一掺杂密度和横向距离Lbe以在1

公开(公告)号：US08455306B2

公开(公告)日：2013-06-04

申请号：US13480924

申请日：2012-05-25

申请人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L21/332 ,  H01L21/00 ,  H01L27/02

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

摘要翻译： 实施例包括用于形成耦合在输入输出（I / O）和核心电路的公共端子之间的静电放电（ESD）保护装置的方法，其中ESD保护装置包括第一和第二合并双极晶体管。 第一晶体管的基极用作第二晶体管的集电极，第二晶体管的基极用作第一晶体管的集电极，基极分别具有第一和第二宽度。 第一电阻耦合在第一晶体管的发射极和基极之间，第二电阻耦合在第二晶体管的发射极和基极之间。 ESD触发电压Vt1和保持电压Vh可以通过选择合适的基极宽度和电阻来独立优化。 通过将Vh增加到大致相等的Vt1，ESD保护更稳健，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压。

公开(公告)号：US20120295414A1

公开(公告)日：2012-11-22

申请号：US13561990

申请日：2012-07-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L21/76 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

摘要翻译： 提供了用于生产叠层静电放电（ESD）夹具的方法。 在一个实施例中，该方法包括提供形成第一和第二串联耦合晶体管的半导体衬底。 第一晶体管包括具有部分地形成第一晶体管的基极的第一侧边缘的第一阱区。 第二晶体管包括具有部分地形成第二晶体管的基极的第二横向边缘的第二阱区。 第三和第四阱区分别形成在第一和第二晶体管中，并且与第一和第二晶体管的阱区相比，延伸到衬底中的不同距离。 第三阱区域具有与第一侧边缘分开第一间隔尺寸D1的第三横向边缘。 第四阱区具有与第二侧边缘分离第二间隔尺寸D2的第四横向边缘，其不同于D1。

公开(公告)号：US20100301389A1

公开(公告)日：2010-12-02

申请号：US12474443

申请日：2009-05-29

申请人： Vadim A. Kushner ,  Amaury Gendron ,  Chai Ean E. Gill

发明人： Vadim A. Kushner ,  Amaury Gendron ,  Chai Ean E. Gill

IPC分类号： H01L29/73

CPC分类号： H01L27/0259

摘要： An electrostatic discharge protection structure includes a first vertical bipolar junction transistor; a second vertical bipolar junction transistor, wherein the second vertical bipolar junction transistor has a common collector with the first vertical bipolar junction transistor, and the common collector has a first conductivity; a horizontal bipolar junction transistor wherein the collector of the horizontal bipolar junction transistor has a second conductivity that is a different conductivity than the first conductivity, and the base of the horizontal bipolar junction transistor is electrically coupled to the common collector of the first vertical bipolar junction transistor and the second vertical bipolar junction transistor; a first avalanche diode electrically coupled to the base and the collector of the first vertical bipolar junction transistor; and a second avalanche diode electrically coupled to the base and the collector of the second vertical bipolar junction transistor.

摘要翻译： 静电放电保护结构包括第一垂直双极结晶体管; 第二垂直双极结晶体管，其中所述第二垂直双极结型晶体管具有与所述第一垂直双极结型晶体管的公共集电极，并且所述公共集电极具有第一导电性; 水平双极结型晶体管，其中水平双极结型晶体管的集电极具有与第一导电性不同的导电率的第二导电性，并且水平双极结型晶体管的基极电耦合到第一垂直双极结的公共集电极 晶体管和第二垂直双极结晶体管; 电耦合到第一垂直双极结晶体管的基极和集电极的第一雪崩二极管; 以及电耦合到第二垂直双极结型晶体管的基极和集电极的第二雪崩二极管。

公开(公告)号：US08921942B2

公开(公告)日：2014-12-30

申请号：US13561990

申请日：2012-07-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L27/02

CPC分类号： H01L27/0259

摘要： Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

摘要翻译： 提供了用于生产叠层静电放电（ESD）夹具的方法。 在一个实施例中，该方法包括提供形成第一和第二串联耦合晶体管的半导体衬底。 第一晶体管包括具有部分地形成第一晶体管的基极的第一侧边缘的第一阱区。 第二晶体管包括具有部分地形成第二晶体管的基极的第二横向边缘的第二阱区。 第三和第四阱区分别形成在第一和第二晶体管中，并且与第一和第二晶体管的阱区相比，延伸到衬底中的不同距离。 第三阱区域具有与第一侧边缘分开第一间隔尺寸D1的第三横向边缘。 第四阱区具有与第二侧边缘分离第二间隔尺寸D2的第四横向边缘，其不同于D1。

公开(公告)号：US08648419B2

公开(公告)日：2014-02-11

申请号：US12690771

申请日：2010-01-20

申请人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

发明人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

IPC分类号： H01L21/331 ,  H01L23/62

CPC分类号： H01L29/66234 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（DeltaVt1）MAX，例如由于半导体晶片或晶片上的晶体管（21,21'，70,700）的不同方位取向是多少 减少 触发电压一致性和制造产量提高。

公开(公告)号：US08390071B2

公开(公告)日：2013-03-05

申请号：US12956686

申请日：2010-11-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L23/62 ,  H01L21/8222

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.

摘要翻译： 用于保护电路芯（24）的可堆叠静电放电（ESD）保护夹具（21）包括：具有基部接触（77）的基极区域（74,51,52,85）的双极晶体管（56,58） 以及与基部触点（77）间隔开横向距离Lbe的发射器（78）和靠近基部区域（74,51,52,85）的收集器（80,86,762）。 基部区域（74,51,52,85）包括包括基部触头（77）和发射极（78）的第一部分（51）和具有与集电器分离的侧边界（752）的第二部分（52） （86,762）由其宽度D控制钳位触发电压的击穿区域（84），第二部分（52）位于第一部分（51）和边界（752）之间。 通过增加发射极 - 基极区（74,51,52,85）的寄生电阻Rbe，例如增加Lbe或减小相对掺杂密度来改善ESD钳位（21）的损伤起始阈值电流It2 的第一部分（51）或其组合。