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11.发明申请Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry 有权使用系数对称的多相插值滤波器的最小面积集成电路实现公开(公告)号：US20060120494A1
公开(公告)日：2006-06-08
申请号：US11215319
申请日：2005-08-29
IPC分类号： H04B1/10
CPC分类号： H03H17/0275 , H03H17/0657
摘要： A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
摘要翻译： 最小面积集成多相插值滤波器使用输入数据通道的系数对称性。 滤波器包括用于使输入信号与第一内部时钟信号同步的输入接口块; 用于提供多个延迟输出信号的存储块; 多路复用器输入接口块，用于响应于第二组内部控制信号输出用于产生镜像系数组的所选择的多个信号，用于产生镜像和/或对称系数集的系数块，以及输出多个滤波器 信号，用于对所述多个滤波信号执行选择，增益控制和数据宽度控制的输出多路复用器块，同步滤波后的信号的输出寄存器块以及用于实现滤波器并在两个通道之间延迟的控制块 以访问系数集合，从而最小化过滤器中的硬件。
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公开(公告)号：US07917569B2
公开(公告)日：2011-03-29
申请号：US11254935
申请日：2005-10-20
申请人： Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
发明人： Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
IPC分类号： G06F7/00
CPC分类号： H03H17/0225
摘要： A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.
摘要翻译： 用于实现产品总和表达式的装置包括接收用于产生第一组部分优化的表达项的系数组/复合和乘积表达式的第一组2-输入移位和加法（2SAD）块 通过在其中应用递归优化，第二组1输入Shift-and-Add（1SAD）块从2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化的表达项，第二组2SAD块 接收来自第一组2SAD块和第二组1SAD块的递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第二组2SAD块从块接收响应以产生 通过应用分解和因式分解的第四组部分优化表达式，以及从第四组接收响应的第五组2SAD块 的2SAD块，用于生成最终输出。
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13.发明授权Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry 有权使用系数对称的多相插值滤波器的最小面积集成电路实现公开(公告)号：US07698355B2
公开(公告)日：2010-04-13
申请号：US11215319
申请日：2005-08-29
CPC分类号： H03H17/0275 , H03H17/0657
摘要： A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
摘要翻译： 最小面积集成多相插值滤波器使用输入数据通道的系数对称性。 滤波器包括用于使输入信号与第一内部时钟信号同步的输入接口块; 用于提供多个延迟输出信号的存储块; 多路复用器输入接口块，用于响应于第二组内部控制信号输出用于产生镜像系数组的所选择的多个信号，用于产生镜像和/或对称系数集的系数块，以及输出多个滤波器 信号，用于对所述多个滤波信号执行选择，增益控制和数据宽度控制的输出多路复用器块，同步滤波后的信号的输出寄存器块以及产生用于实现滤波器的时钟信号并在两个通道之间延迟的控制块 以访问系数集合，从而最小化过滤器中的硬件。
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14.发明授权Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output 有权区域有效实现位串行FIR，IIR滤波器和具有零延迟时钟输出的组合/顺序逻辑结构的系数架构公开(公告)号：US07007053B1
公开(公告)日：2006-02-28
申请号：US09807500
申请日：1998-10-13
申请人： Rakesh Malik , Puneet Goel
发明人： Rakesh Malik , Puneet Goel
IPC分类号： G06F17/10
CPC分类号： H03H17/0223 , H03H17/0225 , H03H17/0227 , H03H2218/08 , H03H2218/10
摘要： An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The coefficient block also enables an area minimal realization of digital filters based on the coefficient block, when operated in serial bit fashion. The optimization techniques and structure are good for bit-serial digital filters typically a finite impulse response (FIR) filter, including finite impulse response filter (IIR) and for other filters and applications based on combinational logic that includes delay elements, multipliers, and serial adders and/or subtractors.
摘要翻译： 系数块的区域有效实现包括应用于该块的硬件共享技术和优化。 该块连接到来自要连接的延迟块的系数线，以执行硬件优化的过滤操作或数学计算操作，并提供零延迟输出。 当以串行位方式操作时，系数块还使得能够基于系数块的数字滤波器的面积最小化实现。 优化技术和结构对于位串行数字滤波器通常是有限脉冲响应（FIR）滤波器，包括有限脉冲响应滤波器（IIR）以及基于组合逻辑的其他滤波器和应用，包括延迟元件，乘法器和串行 加法器和/或减法器。
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