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1.发明申请Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry 有权使用系数对称的多相插值滤波器的最小面积集成电路实现公开(公告)号：US20060120494A1
公开(公告)日：2006-06-08
申请号：US11215319
申请日：2005-08-29
IPC分类号： H04B1/10
CPC分类号： H03H17/0275 , H03H17/0657
摘要： A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
摘要翻译： 最小面积集成多相插值滤波器使用输入数据通道的系数对称性。 滤波器包括用于使输入信号与第一内部时钟信号同步的输入接口块; 用于提供多个延迟输出信号的存储块; 多路复用器输入接口块，用于响应于第二组内部控制信号输出用于产生镜像系数组的所选择的多个信号，用于产生镜像和/或对称系数集的系数块，以及输出多个滤波器 信号，用于对所述多个滤波信号执行选择，增益控制和数据宽度控制的输出多路复用器块，同步滤波后的信号的输出寄存器块以及用于实现滤波器并在两个通道之间延迟的控制块 以访问系数集合，从而最小化过滤器中的硬件。
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2.发明授权Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry 有权使用系数对称的多相插值滤波器的最小面积集成电路实现公开(公告)号：US07698355B2
公开(公告)日：2010-04-13
申请号：US11215319
申请日：2005-08-29
CPC分类号： H03H17/0275 , H03H17/0657
摘要： A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals, an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block synchronizing the filtered signals, and a control block generating clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware in the filter.
摘要翻译： 最小面积集成多相插值滤波器使用输入数据通道的系数对称性。 滤波器包括用于使输入信号与第一内部时钟信号同步的输入接口块; 用于提供多个延迟输出信号的存储块; 多路复用器输入接口块，用于响应于第二组内部控制信号输出用于产生镜像系数组的所选择的多个信号，用于产生镜像和/或对称系数集的系数块，以及输出多个滤波器 信号，用于对所述多个滤波信号执行选择，增益控制和数据宽度控制的输出多路复用器块，同步滤波后的信号的输出寄存器块以及产生用于实现滤波器的时钟信号并在两个通道之间延迟的控制块 以访问系数集合，从而最小化过滤器中的硬件。
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公开(公告)号：US20060153321A1
公开(公告)日：2006-07-13
申请号：US11254935
申请日：2005-10-20
申请人： Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
发明人： Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
IPC分类号： H04B1/10
CPC分类号： H03H17/0225
摘要： A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.
摘要翻译： 用于实现产品总和表达式的装置包括接收用于产生第一组部分优化的表达项的系数组/复合和乘积表达式的第一组2-输入移位和加法（2SAD）块 通过在其中应用递归优化，第二组1输入Shift-and-Add（1SAD）块从2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化的表达项，第二组2SAD块 接收来自第一组2SAD块和第二组1SAD块的递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第二组2SAD块从块接收响应以产生 通过应用分解和因式分解的第四组部分优化表达式，以及从第四组接收响应的第五组2SAD块 的2SAD块，用于生成最终输出。
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公开(公告)号：US07917569B2
公开(公告)日：2011-03-29
申请号：US11254935
申请日：2005-10-20
申请人： Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
发明人： Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
IPC分类号： G06F7/00
CPC分类号： H03H17/0225
摘要： A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.
摘要翻译： 用于实现产品总和表达式的装置包括接收用于产生第一组部分优化的表达项的系数组/复合和乘积表达式的第一组2-输入移位和加法（2SAD）块 通过在其中应用递归优化，第二组1输入Shift-and-Add（1SAD）块从2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化的表达项，第二组2SAD块 接收来自第一组2SAD块和第二组1SAD块的递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第二组2SAD块从块接收响应以产生 通过应用分解和因式分解的第四组部分优化表达式，以及从第四组接收响应的第五组2SAD块 的2SAD块，用于生成最终输出。
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公开(公告)号：US20120158339A1
公开(公告)日：2012-06-21
申请号：US12974409
申请日：2010-12-21
IPC分类号： G06F19/00
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , G06F11/3024 , G06F11/3058 , G11C29/023 , Y02D10/126 , Y02D10/172
摘要： An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.
摘要翻译： 包括至少一个路径，至少一个复制路径，对应于相应路径的所述至少一个复制路径的布置，被配置为使用从所述至少一个复制路径导出的控制信息的控制器，所述至少一个路径包括 监视单元，被配置为向所述控制器提供监视器信息，所述控制器被配置为根据所述监视器信息修改所述控制信息。
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公开(公告)号：US20110068858A1
公开(公告)日：2011-03-24
申请号：US12563058
申请日：2009-09-18
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.
摘要翻译： 片上系统（SoC）具有数字域。 自适应电压/频率缩放电路包括关于该数字域的关键路径复制电路。 关键路径复制电路产生余量信号，并且自适应电压调节电路通过减少施加到片上系统的数字域的偏置电压（和/或增加时钟频率）来响应余量信号，以便恢复可用余量。 故障安全定时传感器包括在片上系统的数字域中。 当数字域内的定时标准被违反时，定时传感器产生一个标志信号。 自适应电压缩放电路通过增加施加到片上系统的数字域的偏置电压（和/或降低时钟频率）来响应标志信号，以便实现恢复操作。
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7.发明授权Adaptive multi-stage slack borrowing for high performance error resilient computing 有权用于高性能错误弹性计算的自适应多级松弛借贷公开(公告)号：US08552765B2
公开(公告)日：2013-10-08
申请号：US13174078
申请日：2011-06-30
IPC分类号： G01R29/02
CPC分类号： H03K3/02 , H03K3/0375
摘要： Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.
摘要翻译： 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。
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公开(公告)号：US08269545B2
公开(公告)日：2012-09-18
申请号：US13285541
申请日：2011-10-31
IPC分类号： H03H11/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.
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公开(公告)号：US20080129351A1
公开(公告)日：2008-06-05
申请号：US11803725
申请日：2007-05-15
申请人： Nitin Chawla
发明人： Nitin Chawla
CPC分类号： H04B1/69 , H03C3/0925 , H03C3/0933 , H03L7/1976 , H03M7/3026 , H03M7/3042
摘要： The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required noise transfer function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band signal-to-noise ratio (SNR) at the cost of higher out-of-band noise.
摘要翻译： 本公开提供了具有数字控制的锁相环（PLL）和数字频率分布生成器的扩频时钟生成系统，以便为了实现输出调制时钟的频谱平坦度而创建近似最佳的频率调制曲线。 该电路与多级误差反馈噪声整形结构相结合，为结构量化噪声提供所需的噪声传递函数，但保持单位增益全通信号传递功能。 这种布置以较高的带外噪声为代价降低了带内信噪比（SNR）的降低。
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10.发明申请ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING 有权适用于高性能误差计算的自适应多级滑块公开(公告)号：US20120176173A1
公开(公告)日：2012-07-12
申请号：US13174078
申请日：2011-06-30
CPC分类号： H03K3/02 , H03K3/0375
摘要： Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.
摘要翻译： 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。
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