Transaction elimination using metadata

    公开(公告)号:US10114585B2

    公开(公告)日:2018-10-30

    申请号:US15448203

    申请日:2017-03-02

    Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

    Runtime Optimization of Multi-core System Designs for Increased Operating Life and Maximized Performance
    13.
    发明申请
    Runtime Optimization of Multi-core System Designs for Increased Operating Life and Maximized Performance 审中-公开
    多核系统设计的运行时优化,提高运行寿命和最大化性能

    公开(公告)号:US20150169363A1

    公开(公告)日:2015-06-18

    申请号:US14563333

    申请日:2014-12-08

    CPC classification number: G06F9/4893 G06F9/4818 G06F9/4881 Y02D10/24

    Abstract: Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system. In an aspect, a reliability engine may be configured to determine priorities for a selected cluster of processor cores according to various methods depending on whether the selected processor cores are inactive and/or whether the computing device is in a cold boot state. The reliability engine may be configured to determine the priorities according to a round robin scheme, a pseudorandom scheme, from stored and/or collected operation data, or from stored and/or collected built in self test data in response to various activities and boot states of the processor cores. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores.

    Abstract translation: 方面包括用于在多核处理系统中调整任务分配给处理器核心的计算设备,系统和方法。 在一方面,可靠性引擎可以被配置为根据所选择的处理器核是不活动的和/或计算设备是否处于冷引导状态,根据各种方法来确定所选择的处理器核心簇的优先级。 可靠性引擎可以被配置为响应于各种活动和引导状态,根据来自存储和/或收集的操作数据的循环方案,伪随机方案或来自存储和/或收集的内置自检数据来确定优先级 的处理器内核。 可靠性引擎可以根据等效处理器核心的优先级重新排列虚拟处理器识别转换表。

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