Abstract:
The disclosure relates to an apparatus including a receiver configured to process a radio frequency (RF) signal to generate a baseband signal; a radio frequency (RF) jammer detector configured to generate a signal indicative of whether an RF jammer is present at an input of the receiver; and a receiver bias circuit configured to generate a supply voltage for the receiver based on the RF jammer indication signal. In another aspect, the apparatus includes constant gain bias circuit to maintain the gain of the receiver constant in response to changes in the supply voltage. In other aspects, the receiver bias circuit may suspend the generating of the supply voltage based on the RF jammer indication signal if the power level of the target received signal is above a threshold. In other aspects, the receiver bias circuit changes the supply voltage during cyclic prefix (CP) intervals between downlink intervals.
Abstract:
A programmable filter includes a first programmable filter instance comprising a first adjustable active inductance capacitively coupled to a signal receive path, the capacitive coupling comprising at least one adjustable capacitance, the adjustable active inductance and the at least one adjustable capacitance configurable to provide a filter response at a first selected frequency, and a second programmable filter instance comprising a second adjustable active inductance capacitively coupled to the signal receive path, the capacitive coupling comprising at least one adjustable capacitance, the second adjustable active inductance and the at least one adjustable capacitance configurable to provide a filter response at a second selected frequency.
Abstract:
Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.