公开(公告)号：US10418333B1

公开(公告)日：2019-09-17

申请号：US15985978

申请日：2018-05-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Manuel Aldrete

IPC: H01L29/82 ,  H01L21/00 ,  H01L23/552 ,  H01L23/66

Abstract: Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes an IC and a shielding sidewall disposed adjacent to the IC. In certain aspects, the IC comprises a first layer coupled to the shielding sidewall, a second layer comprising a first signal path, and a third layer disposed below the first layer and coupled to the shielding sidewall, wherein the second layer is disposed between the first layer and the third layer. In some cases, the IC also includes a plurality of vias configured to couple the first layer to the third layer, wherein at least a portion of the first signal path is disposed in an inner shielding region that spans from the first layer to the third layer and spans from the shielding sidewall to the plurality of vias.

公开(公告)号：US09466578B2

公开(公告)日：2016-10-11

申请号：US14251518

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Manuel Aldrete ,  Milind Pravin Shah

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/03 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract translation: 一些新颖的特征涉及包括基板，第一通孔和第一凸块焊盘的集成装置。 第一个通孔穿过基板。 第一个通孔具有第一通孔尺寸。 第一凸块焊盘位于基板的表面上。 第一碰撞焊盘耦合到第一通孔。 第一凸块焊盘具有等于或小于第一通孔尺寸的第一焊盘尺寸。 在一些实施方案中，集成器件包括第二通孔和第二凸点焊盘。 第二个通孔穿过基板。 第二通孔具有第二通孔尺寸。 第二凸点焊盘位于基板的表面上。 第二凸点焊盘耦合到第二通孔。 第二凸块焊盘具有等于或小于第二通孔尺寸的第二焊盘尺寸。