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公开(公告)号:US20190252296A1
公开(公告)日:2019-08-15
申请号:US16390138
申请日:2019-04-22
发明人: Jui-Pin Hung , Jing-Cheng Lin , Po-Hao Tsai , Yi-Jou Lin , Shuo-Mao Chen , Chiung-Han Yeh , Der-Chyang Yeh
IPC分类号: H01L23/48 , H01L25/065 , H01L23/538 , H01L23/00 , H01L25/10 , H01L21/56 , H01L21/768 , H01L21/82 , H01L25/18 , H01L25/00 , H01L23/31 , H01L21/48 , H01L23/28 , H01L23/498 , H01L23/528
CPC分类号: H01L23/481 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/76843 , H01L21/82 , H01L23/28 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/528 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L24/73 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/83 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2924/00 , H01L2224/82
摘要: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
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公开(公告)号:US20190244871A1
公开(公告)日:2019-08-08
申请号:US16390482
申请日:2019-04-22
发明人: Chen-Hua Yu , Kuo-Chung Yee , Hao-Yi Tsai , Tin-Hao Kuo
CPC分类号: H01L23/3114 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/295 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/14181 , H01L2224/16227 , H01L2224/16265 , H01L2224/214 , H01L2224/24137 , H01L2224/24147 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73217 , H01L2224/73267 , H01L2224/81005 , H01L2224/9222 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2924/1431 , H01L2924/1434 , H01L2924/18162 , H01L2924/19041 , H01L2224/83 , H01L2224/19 , H01L2224/83005
摘要: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
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3.
公开(公告)号:US20190221533A1
公开(公告)日:2019-07-18
申请号:US16246912
申请日:2019-01-14
发明人: Horst THEUSS , Rudolf BERGER , Walter HARTNER , Veronika HUBER , Werner ROBL
IPC分类号: H01L23/00 , H01L23/498 , H01L21/48
CPC分类号: H01L24/05 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0231 , H01L2224/0239 , H01L2224/03462 , H01L2224/03848 , H01L2224/0401 , H01L2224/05647 , H01L2224/13023 , H01L2224/13024 , H01L2224/13147 , H01L2224/16227 , H01L2924/3512
摘要: A semiconductor device includes a semiconductor chip, an electrical connection element for electrically connecting the semiconductor device to a carrier, and a metallization adjoining the electrical connection element, the metallization contains porous nanocrystalline copper that contains portions of organic acids.
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公开(公告)号:US20190214503A1
公开(公告)日:2019-07-11
申请号:US16045125
申请日:2018-07-25
发明人: MingJiue YU , YuanJun HSU
IPC分类号: H01L29/786 , H01L29/417 , H01L29/423 , H01L29/66 , H01L23/532 , H01L21/02 , H01L21/48
CPC分类号: H01L29/78618 , H01L21/02123 , H01L21/02304 , H01L21/486 , H01L23/5329 , H01L27/3258 , H01L29/41733 , H01L29/42384 , H01L29/66742
摘要: A P-type thin-film transistor and manufacturing method are provided. The method includes: forming an active layer having a P-type material on a buffering layer; forming a gate insulation layer on the active layer; depositing a gate metal layer on the gate insulation layer; forming a photoresist layer on the gate metal layer, and patterning the photoresist layer; etching the gate metal layer to form a gate electrode such that a projection of the gate electrode is within the patterned photoresist layer; using the patterned photoresist layer as a barrier layer to etch the gate insulation layer such that a projection of the gate electrode is within the gate insulation layer, and a projection of the gate insulation layer is within the active layer; doping two side regions of the active layer located below the gate insulation layer; and forming a source electrode and drain electrode on the doped regions.
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公开(公告)号:US20190200455A1
公开(公告)日:2019-06-27
申请号:US16286237
申请日:2019-02-26
申请人: Ajinomoto Co., Inc.
发明人: Shigeo NAKAMURA , Shiro TATSUMI , lkumi SAWA
IPC分类号: H05K1/03 , H05K3/46 , C08L63/00 , H05K3/22 , H01L23/14 , H01L21/48 , H05K3/00 , B32B27/00 , H01L21/683 , H01L23/498
CPC分类号: H05K1/0373 , B32B7/04 , B32B15/08 , B32B15/20 , B32B27/00 , B32B27/08 , B32B27/10 , B32B27/18 , B32B27/205 , B32B27/26 , B32B27/28 , B32B27/281 , B32B27/285 , B32B27/288 , B32B27/32 , B32B27/325 , B32B27/36 , B32B27/365 , B32B2264/02 , B32B2264/0207 , B32B2264/0264 , B32B2307/202 , B32B2307/206 , B32B2307/306 , B32B2307/7265 , B32B2307/732 , B32B2457/08 , C08G59/621 , C08G59/686 , C08L63/00 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/145 , H01L23/49894 , H01L2221/68345 , H05K3/0011 , H05K3/22 , H05K3/4038 , H05K3/4673 , H05K3/4682 , H05K2201/0209 , H05K2201/0212 , H05K2203/06
摘要: Resin sheets which includes a support and a resin composition layer in contact on the support, and which are characterized in that an extracted water conductivity A of a cured product of the resin composition layer when extracted at 120° C. for 20 hours is 50 μS/cm or less and an extracted water conductivity B of the cured product of the resin composition layer when extracted at 160° C. for 20 hours is 200 μS/cm or less, can provide a thin insulating layer having excellent insulating properties.
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6.
公开(公告)号:US20190189599A1
公开(公告)日:2019-06-20
申请号:US15847242
申请日:2017-12-19
发明人: Bora Baloglu , Ron Huemoeller , Curtis Zwenger
IPC分类号: H01L25/10 , H01L23/367 , H01L23/373 , H01L23/538 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/552 , H01L23/00
CPC分类号: H01L25/105 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4882 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/3672 , H01L23/3675 , H01L23/3677 , H01L23/3736 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L23/552 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/13082 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/214 , H01L2224/32135 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/81005 , H01L2224/81203 , H01L2224/81224 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H01L2924/3511 , H01L2224/81 , H01L2924/014 , H01L2924/00014
摘要: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.
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公开(公告)号:US20190157242A1
公开(公告)日:2019-05-23
申请号:US16092917
申请日:2017-04-07
发明人: Heinz Moitzi , Dietmar Drofenik
IPC分类号: H01L23/00 , H01L21/48 , H01L21/683 , H01L23/31 , H01L21/56 , H01L23/498
CPC分类号: H01L24/97 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49822 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/20 , H01L24/94 , H01L2221/68345 , H01L2221/68359 , H01L2221/68372 , H01L2224/0231 , H01L2224/02371 , H01L2224/02379 , H01L2224/03002 , H01L2224/04042 , H01L2224/04105 , H01L2224/05548 , H01L2224/06181 , H01L2224/08225 , H01L2224/211 , H01L2224/2518 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2224/95001 , H01L2924/14 , H01L2924/1427 , H01L2924/1431 , H01L2924/1434 , H01L2924/3025 , H01L2924/3511 , H01L2924/00014 , H01L2224/023 , H01L2924/00012
摘要: A method of manufacturing a batch of component carriers is disclosed. The method includes providing a plurality of separate wafer structures, each comprising a plurality of electronic components, simultaneously laminating the wafer structures with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and singularizing a structure resulting from the laminating into the plurality of component carriers, each comprising at least one of the electronic components, a part of the at least one electrically conductive layer structure and a part of the at least one electrically insulating layer structure.
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8.
公开(公告)号:US20190131230A1
公开(公告)日:2019-05-02
申请号:US16220148
申请日:2018-12-14
发明人: Ta-Pen Guo , Carlos H. Diaz , Jean-Pierre Colinge , Yi-Hsiung Lin
IPC分类号: H01L23/498 , H01L23/48 , H01L27/06 , H01L21/48 , H01L27/092
CPC分类号: H01L23/49827 , H01L21/4846 , H01L21/486 , H01L23/481 , H01L23/498 , H01L23/49844 , H01L27/0688 , H01L27/092
摘要: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.
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公开(公告)号:US20190096798A1
公开(公告)日:2019-03-28
申请号:US15718012
申请日:2017-09-28
申请人: Intel Corporation
发明人: Aleksandar Aleksov , Arnab Sarkar , Arghya Sain , Kristof Darmawikarta , Henning Braunisch , Prashant D. Parmar , Sujit Sharan , Johanna M. Swan , Feras Eid
IPC分类号: H01L23/50 , H01L21/48 , H01L23/498
CPC分类号: H01L23/50 , G06F17/5068 , G06F17/5077 , G06F2217/40 , H01L21/4853 , H01L21/486 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L23/5225 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/13022 , H01L2224/131 , H01L2224/16145 , H01L2924/1434 , H01L2924/15311 , H01L2924/3011 , H01L2924/014 , H01L2924/00014
摘要: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.
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公开(公告)号:US20190088566A1
公开(公告)日:2019-03-21
申请号:US15895604
申请日:2018-02-13
发明人: Seung Soo HA , Hyeon Seok LEE , Sun Ho KIM
IPC分类号: H01L23/31 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/498
CPC分类号: H01L23/3128 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L23/3114 , H01L23/49816 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16235 , H01L2224/16238 , H01L2224/18 , H05K1/185 , H01L2924/00015 , H01L2924/0001
摘要: A fan-out semiconductor package includes a core member having a through-hole. A semiconductor chip is in the through-hole and has an active surface with connection pads and an inactive surface opposing the active surface. An encapsulant encapsulates at least portions of the core member and the semiconductor chip and fills at least a portion of the through-hole. A connection member is on the core member and the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads. The core member includes a groove portion penetrating from a wall of the through-hole up to an outer side surface of the core member in a lower portion of the core member on which the connection member is disposed.
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