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    Backside drill embedded die substrate
    1.
    发明授权
    Backside drill embedded die substrate 有权

    公开(公告)号：US10325855B2

    公开(公告)日：2019-06-18

    申请号：US15074750

    申请日：2016-03-18

    Applicant: QUALCOMM Incorporated

    Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

    IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

    Waveguide along shielded side wall
    7.
    发明授权
    Waveguide along shielded side wall 有权

    公开(公告)号：US10418333B1

    公开(公告)日：2019-09-17

    申请号：US15985978

    申请日：2018-05-22

    Applicant: QUALCOMM Incorporated

    Inventor： Daeik Kim ,  Jie Fu ,  Manuel Aldrete

    IPC: H01L29/82 ,  H01L21/00 ,  H01L23/552 ,  H01L23/66

    Abstract: Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes an IC and a shielding sidewall disposed adjacent to the IC. In certain aspects, the IC comprises a first layer coupled to the shielding sidewall, a second layer comprising a first signal path, and a third layer disposed below the first layer and coupled to the shielding sidewall, wherein the second layer is disposed between the first layer and the third layer. In some cases, the IC also includes a plurality of vias configured to couple the first layer to the third layer, wherein at least a portion of the first signal path is disposed in an inner shielding region that spans from the first layer to the third layer and spans from the shielding sidewall to the plurality of vias.

    Substrate comprising improved via pad placement in bump area
    8.
    发明授权
    Substrate comprising improved via pad placement in bump area 有权
    衬底包括在凸起区域中改进的通孔焊盘放置

    公开(公告)号：US09466578B2

    公开(公告)日：2016-10-11

    申请号：US14251518

    申请日：2014-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Jie Fu ,  Manuel Aldrete ,  Milind Pravin Shah

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    CPC classification number: H01L24/03 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00

    Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

    Abstract translation: 一些新颖的特征涉及包括基板，第一通孔和第一凸块焊盘的集成装置。 第一个通孔穿过基板。 第一个通孔具有第一通孔尺寸。 第一凸块焊盘位于基板的表面上。 第一碰撞焊盘耦合到第一通孔。 第一凸块焊盘具有等于或小于第一通孔尺寸的第一焊盘尺寸。 在一些实施方案中，集成器件包括第二通孔和第二凸点焊盘。 第二个通孔穿过基板。 第二通孔具有第二通孔尺寸。 第二凸点焊盘位于基板的表面上。 第二凸点焊盘耦合到第二通孔。 第二凸块焊盘具有等于或小于第二通孔尺寸的第二焊盘尺寸。

    PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD
    10.
    发明申请
    PACKAGE HAVING THERMAL COMPRESSION FLIP CHIP (TCFC) AND CHIP WITH REFLOW BONDING ON LEAD 审中-公开
    具有热压缩芯片（TCFC）和芯片的包装与引导连接

    公开(公告)号：US20140159238A1

    公开(公告)日：2014-06-12

    申请号：US13708221

    申请日：2012-12-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： Manuel Aldrete ,  Milind P. Shah ,  Omar J. Bchir ,  Houssam W. Jomaa ,  Chin-Kwan Kim

    IPC: H01L23/488 ,  H01L23/00

    CPC classification number: H01L23/488 ,  H01L21/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.

    Abstract translation: 本公开的一些示例性实施方式涉及包括基板，第一管芯和第二管芯的集成电路封装。 衬底包括第一组迹线和第二组迹线。 第一组轨迹具有第一音调。 第二组轨迹具有第二个间距。 第一节距小于第二节距。 在一些实施方案中，一组迹线的间距限定了两个相邻迹线之间的中心到中心距离，或者衬底上的接合焊盘。 第一管芯通过热压接工艺耦合到衬底。 在一些实施方式中，第一管芯耦合到衬底的第一组迹线。 第二管芯通过回流焊接工艺耦合到衬底。 在一些实施方式中，第二管芯耦合到衬底的第二组迹线。

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