Patent search ap:("QUALCOMM Incorporated") AND inv:"Kun Fang" Page 2

11.

发明授权
Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same 有权

公开(公告)号：US11869833B2

公开(公告)日：2024-01-09

申请号：US17476383

申请日：2021-09-15

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang , Jaehyun Yeon , Suhyung Hwang , Hyunchul Cho

IPC: H01L23/498 , H01L21/48 , H01L23/31 , H01L23/00

CPC classification number: H01L23/49822 , H01L21/4857 , H01L23/49838 , H01L23/3128 , H01L24/16 , H01L2224/16227

Abstract: A package that includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a first via interconnect and a first trace interconnect, wherein the first via interconnect is directly coupled to the first trace interconnect. The first via interconnect is coupled to the first trace interconnect without an intervening pad interconnect between the first via interconnect and the first trace interconnect.

12.

发明授权
Package with a substrate comprising pad-on-pad interconnects 有权

公开(公告)号：US11823983B2

公开(公告)日：2023-11-21

申请号：US17210314

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang , Jaehyun Yeon , Suhyung Hwang , Hong Bok We

IPC: H01L23/482 , H01L23/522 , H01L23/528

CPC classification number: H01L23/482 , H01L23/528 , H01L23/5226

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises at least one dielectric layer; a plurality of interconnects comprising plurality of pad-on-pad interconnects, wherein the plurality of pad-on-pad interconnects is embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect comprising a first pad and a second pad coupled to the first pad. The package further comprising a solder resist layer located over the first surface of the substrate. The solder resist layer comprises a first solder resist layer portion comprising a first thickness; and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The second solder resist layer portion is located between the at least one dielectric layer and the integrated device.

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