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公开(公告)号:US20230307817A1
公开(公告)日:2023-09-28
申请号:US17651324
申请日:2022-02-16
Applicant: QUALCOMM Incorporated
Inventor: Suhyung Hwang , Kun Fang , Jaehyun Yeon , Chin-Kwan Kim , Taesik Yang
CPC classification number: H01Q1/2283 , H01Q9/045 , H01Q21/065
Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radiofrequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.
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公开(公告)号:US11183446B1
公开(公告)日:2021-11-23
申请号:US16994910
申请日:2020-08-17
Applicant: QUALCOMM Incorporated
Inventor: Jaehyun Yeon , Suhyung Hwang , Hong Bok We , Kun Fang
IPC: H05K1/02 , H01L23/498 , H05K1/11 , H05K3/40 , H05K3/10
Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.
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公开(公告)号:US12300873B2
公开(公告)日:2025-05-13
申请号:US17651324
申请日:2022-02-16
Applicant: QUALCOMM Incorporated
Inventor: Suhyung Hwang , Kun Fang , Jaehyun Yeon , Chin-Kwan Kim , Taesik Yang
Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.
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公开(公告)号:US20230014567A1
公开(公告)日:2023-01-19
申请号:US17375289
申请日:2021-07-14
Applicant: QUALCOMM Incorporated
Inventor: Jaehyun Yeon , Kun Fang , Suhyung Hwang , Hyunchul Cho
IPC: H01Q1/22 , H01Q13/10 , H01L23/498 , H01L23/552 , H01L23/66 , H01L21/48
Abstract: Package substrates employing integrated slot-shaped antenna(s), and related integrated circuit (IC) packages and fabrication methods. The package substrate can be provided in a radio-frequency (RF) IC (RFIC) package. The package substrate includes one or more slot-shaped antennas each formed from a slot disposed in the metallization substrate that can be coupled to the RFIC die for receiving and radiating RF signals. The slot-shaped antenna includes a conductive slot disposed in at least one metallization layer in the package substrate. A metal interconnect in a metallization layer in the package substrate is coupled to the conductive slot to provide an antenna feed line for the slot-shaped antenna. In this manner, the slot-shaped antenna being integrated into the metallization substrate of the IC package can reduce the area in the IC package needed to provide an antenna and/or provide other directions of antenna radiation patterns for enhanced directional RF performance.
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公开(公告)号:US11551939B2
公开(公告)日:2023-01-10
申请号:US17010693
申请日:2020-09-02
Applicant: QUALCOMM Incorporated
Inventor: Kun Fang , Jaehyun Yeon , Suhyung Hwang , Hong Bok We
IPC: H01L21/48 , H01L23/498 , H01L23/00
Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.
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公开(公告)号:US20230282959A1
公开(公告)日:2023-09-07
申请号:US17653061
申请日:2022-03-01
Applicant: QUALCOMM Incorporated
Inventor: Jaehyun Yeon , Kun Fang , Suhyung Hwang , Hyunchul Cho
CPC classification number: H01Q1/2283 , H01Q1/2208 , H01Q1/422
Abstract: Multi-directional antenna modules employing a surface-mount antenna(s) to support antenna pattern mufti-directionality, and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and multiple antennas in the package substrate. To provide multi-directionality in antenna radiation patterns, a first antenna is provided that is coupled to the package substrate and oriented in a first plane, and a second antenna is provided that coupled to the package substrate and oriented in a second plane orthogonal to the first plane. In an example, the second antenna is packaged in an antenna package that includes external metal pads that when surface mounted to the package substrate, cause the second antenna to oriented in the second plane.
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公开(公告)号:US11545425B2
公开(公告)日:2023-01-03
申请号:US17066318
申请日:2020-10-08
Applicant: QUALCOMM Incorporated
Inventor: Kun Fang , Jaehyun Yeon , Suhyung Hwang , Hong Bok We
IPC: H01L23/498 , H01L23/00 , H01L21/48
Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.
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公开(公告)号:US11439008B2
公开(公告)日:2022-09-06
申请号:US17149498
申请日:2021-01-14
Applicant: QUALCOMM Incorporated
Inventor: Kun Fang , Jaehyun Yeon , Suhyung Hwang , Hyunchul Cho , Boyu Tseng
Abstract: A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.
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公开(公告)号:US12126071B2
公开(公告)日:2024-10-22
申请号:US17653061
申请日:2022-03-01
Applicant: QUALCOMM Incorporated
Inventor: Jaehyun Yeon , Kun Fang , Suhyung Hwang , Hyunchul Cho
CPC classification number: H01Q1/2283 , H01Q9/0414 , H01Q21/08 , H01Q23/00
Abstract: Multi-directional antenna modules employing a surface-mount antenna(s) to support antenna pattern mufti-directionality, and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and multiple antennas in the package substrate. To provide multi-directionality in antenna radiation patterns, a first antenna is provided that is coupled to the package substrate and oriented in a first plane, and a second antenna is provided that coupled to the package substrate and oriented in a second plane orthogonal to the first plane. In an example, the second antenna is packaged in an antenna package that includes external metal pads that when surface mounted to the package substrate, cause the second antenna to oriented in the second plane.
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公开(公告)号:US12125742B2
公开(公告)日:2024-10-22
申请号:US17479691
申请日:2021-09-20
Applicant: QUALCOMM Incorporated
Inventor: Hyunchul Cho , Kun Fang , Jaehyun Yeon , Suhyung Hwang
IPC: H01L21/768 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/498
CPC classification number: H01L21/76816 , H01L21/486 , H01L21/56 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/81 , H01L2224/04105 , H01L2224/16227
Abstract: A package that includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high-density interconnects located in the at least one dielectric layer and through a first surface of the at least one dielectric layer; a second plurality of high-density interconnects located in the at least one dielectric.
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