公开(公告)号：US09515856B2

公开(公告)日：2016-12-06

申请号：US14720518

申请日：2015-05-22

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Jason Chia-Jen Wei ,  Aliazam Abbasfar

IPC: H04L25/03 ,  H04B1/12

CPC classification number: H04L25/03057 ,  H04B1/123 ,  H04L25/03063 ,  H04L25/03885

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

公开(公告)号：US20150103876A1

公开(公告)日：2015-04-16

申请号：US14575985

申请日：2014-12-18

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H04L25/03

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract translation: 部分响应判决反馈均衡器（PrDFE）包括至少包括第一和第二比较器的接收器，该第一和第二比较器可操作以将表示符号序列的输入信号与相应阈值进行比较，并且分别产生第一和第二接收器输出。 提供第一选择级，以根据第一定时信号在第一比较器输出和第一解析符号之间选择（a），以及（b）根据第一定时信号在第二比较器输出和第一解析符号之间选择 产生相应的第一和第二选择输出。 第二选择阶段根据选择信号在第一和第二选择输出之间进行选择。 选择信号取决于序列中第一个已解析符号之前的先前解析符号。

公开(公告)号：US20130275828A1

公开(公告)日：2013-10-17

申请号：US13850008

申请日：2013-03-25

Applicant: RAMBUS INC.

Inventor： Aliazam Abbasfar

IPC: G06F11/07

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: A circuit, wherein an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. An error-detection circuit coupled to the encoder circuit generates and stores error-detection information associated with the set of M symbols, facilitating subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. A receiver circuit receives feedback information from the other circuit, which includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Control logic performs remedial action based on the feedback information.

Abstract translation: 一种电路，其中编码器电路将一组N个符号编码为代码空间中的给定码字，其中给定码字包括一组M个符号。 M个驱动器耦合到编码器电路并且耦合到信道中的M个链路，其中给定的驱动器将M个符号集合中的给定符号输出到给定的链路上。 耦合到编码器电路的错误检测电路产生并存储与该M个符号集合相关联的错误检测信息，有助于在将该M个符号集合通信给另一个电路期间的误差类型的随后概率确定。 接收器电路从另一电路接收反馈信息，其中包括关于基于代码空间的特征检测M个符号集合中的另一种类型的错误的错误信息。 控制逻辑根据反馈信息执行补救措施。

公开(公告)号：US09479363B2

公开(公告)日：2016-10-25

申请号：US14937558

申请日：2015-11-10

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03 ,  H04L25/497 ,  H03K5/135 ,  H03K5/15

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

公开(公告)号：US09459952B2

公开(公告)日：2016-10-04

申请号：US14567819

申请日：2014-12-11

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/10 ,  G06F11/07

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: A method of operation in a memory controller is disclosed. The method includes generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word. The selectively DBI-encoded data word is for transfer to a memory device. Second error information associated with the selectively DBI-encoded data word is received from the memory device. Errors in the data word are detected by comparing the first error information to the second error information. The detecting includes evaluating the DBI-encoding of the selectively DBI-encoded data word.

Abstract translation: 公开了一种在存储器控制器中的操作方法。 该方法包括为有选择地动态总线反转（DBI）编码的数据字生成第一错误信息。 有选择地DBI编码的数据字用于传送到存储器件。 从存储器件接收与选择性DBI编码的数据字相关联的第二错误信息。 通过将第一错误信息与第二错误信息进行比较来检测数据字中的错误。 该检测包括评估选择性DBI编码的数据字的DBI编码。

公开(公告)号：US20150095748A1

公开(公告)日：2015-04-02

申请号：US14567819

申请日：2014-12-11

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: G06F11/08

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: A method of operation in a memory controller is disclosed. The method includes generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word. The selectively DBI-encoded data word is for transfer to a memory device. Second error information associated with the selectively DBI-encoded data word is received from the memory device. Errors in the data word are detected by comparing the first error information to the second error information. The detecting includes evaluating the DBI-encoding of the selectively DBI-encoded data word.

Abstract translation: 公开了一种在存储器控制器中的操作方法。 该方法包括为有选择地动态总线反转（DBI）编码的数据字生成第一错误信息。 有选择地DBI编码的数据字用于传送到存储器件。 从存储器件接收与选择性DBI编码的数据字相关联的第二错误信息。 通过将第一错误信息与第二错误信息进行比较来检测数据字中的错误。 该检测包括评估选择性DBI编码的数据字的DBI编码。

公开(公告)号：US20140286450A1

公开(公告)日：2014-09-25

申请号：US14065420

申请日：2013-10-29

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar ,  Abbas Komijani

IPC: H04B7/06

CPC classification number: H04B7/06 ,  H04L27/2614 ,  H04L27/2628

Abstract: Embodiments of a communication circuit are described. This communication circuit includes an input node to receive a set of data symbols and a partitioner coupled to the input node. This partitioner is to divide the set of data symbols into M irregular subgroups of data symbols, a given one of which includes non-consecutive data symbols in the set of data symbols. Moreover, this given irregular subgroup of data symbols includes at least two pairs of adjacent data symbols having different inter-data-symbol spacings in the set of data symbols. This communication circuit also includes M modulators coupled to the partitioner, where the given irregular subgroup of data symbols is coupled to a given modulator in the M modulators. Furthermore, the communication circuit includes M output nodes, where a given output node in the M output nodes is coupled to the given modulator and is to couple to an antenna element in M antenna elements.

Abstract translation: 描述通信电路的实施例。 该通信电路包括用于接收一组数据符号的输入节点和耦合到输入节点的分割器。 该分割器将数据符号组划分成M个不规则的数据符号子组，其中一个给定的数据符号包括该组数据符号中的非连续的数据符号。 此外，该给定的不规则数据符号子组包括在该组数据符号中具有不同的数据间符号间隔的至少两对相邻数据符号。 该通信电路还包括耦合到分割器的M个调制器，其中给定的不规则子数据符号耦合到M个调制器中的给定调制器。 此外，通信电路包括M个输出节点，其中M个输出节点中的给定输出节点耦合到给定的调制器，并且耦合到M个天线元件中的天线元件。

公开(公告)号：US20130300482A1

公开(公告)日：2013-11-14

申请号：US13729831

申请日：2012-12-28

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US20160134440A1

公开(公告)日：2016-05-12

申请号：US14937558

申请日：2015-11-10

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03 ,  H03K5/15

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US08630336B2

公开(公告)日：2014-01-14

申请号：US13729831

申请日：2012-12-28

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H03H7/30

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。