公开(公告)号：US09432227B2

公开(公告)日：2016-08-30

申请号：US14575985

申请日：2014-12-18

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H03K5/159 ,  H04L25/03 ,  H03K5/24

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

公开(公告)号：US20150333938A1

公开(公告)日：2015-11-19

申请号：US14720518

申请日：2015-05-22

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Jason Chia-Jen Wei ,  Aliazam Abbasfar

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04B1/123 ,  H04L25/03063 ,  H04L25/03885

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract translation: 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。

公开(公告)号：US08937994B2

公开(公告)日：2015-01-20

申请号：US13915290

申请日：2013-06-11

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H03H7/30 ,  H03K5/24

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract translation: 部分响应判决反馈均衡器（PrDFE）包括至少包括第一和第二比较器的接收器，该第一和第二比较器可操作以将表示符号序列的输入信号与相应阈值进行比较，并且分别产生第一和第二接收器输出。 提供第一选择级，以根据第一定时信号在第一比较器输出和第一解析符号之间选择（a），以及（b）根据第一定时信号在第二比较器输出和第一解析符号之间选择 产生相应的第一和第二选择输出。 第二选择阶段根据选择信号在第一和第二选择输出之间进行选择。 选择信号取决于序列中第一个已解析符号之前的先前解析符号。

公开(公告)号：US20140307833A1

公开(公告)日：2014-10-16

申请号：US14101274

申请日：2013-12-09

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar ,  Farshid Aryanfar

IPC: H04L27/20

CPC classification number: H04L27/22 ,  H04B1/16 ,  H04L27/2014 ,  H04L27/2082

Abstract: Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal.

Abstract translation: 描述电路的实施例。 在该电路中，调制电路提供第一调制电信号和第二调制电信号，其中可以是第一调制电信号或第二调制电信号的给定调制电信号包括最小位移键控（MSK ）调制数据。 此外，耦合到调制电路的第一相位调整元件基于第一相位调整元件的相位值来设定第一调制电信号和第二调制电信号之间的相对相位。 另外，耦合到第一相位调整元件的输出接口耦合到输出信号的一个或多个天线元件。 这些信号包括对应于第一调制电信号和第二调制电信号的正交相移键控（QPSK）信号。

公开(公告)号：US09215103B2

公开(公告)日：2015-12-15

申请号：US14705761

申请日：2015-05-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L27/01 ,  H04L25/03 ,  H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

公开(公告)号：US20150304136A1

公开(公告)日：2015-10-22

申请号：US14705761

申请日：2015-05-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03 ,  H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US09054907B2

公开(公告)日：2015-06-09

申请号：US14148470

申请日：2014-01-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03 ,  H04L25/497 ,  H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US08943382B2

公开(公告)日：2015-01-27

申请号：US13850008

申请日：2013-03-25

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H03M13/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: A circuit, wherein an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. An error-detection circuit coupled to the encoder circuit generates and stores error-detection information associated with the set of M symbols, facilitating subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. A receiver circuit receives feedback information from the other circuit, which includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Control logic performs remedial action based on the feedback information.

Abstract translation: 一种电路，其中编码器电路将一组N个符号编码为代码空间中的给定码字，其中给定码字包括一组M个符号。 M个驱动器耦合到编码器电路并且耦合到信道中的M个链路，其中给定的驱动器将M个符号集合中的给定符号输出到给定的链路上。 耦合到编码器电路的错误检测电路产生并存储与该M个符号集合相关联的错误检测信息，有助于在将该M个符号集合通信给另一个电路期间的误差类型的随后概率确定。 接收器电路从另一电路接收反馈信息，其中包括关于基于代码空间的特征检测M个符号集合中的另一种类型的错误的错误信息。 控制逻辑根据反馈信息执行补救措施。

公开(公告)号：US20140247911A1

公开(公告)日：2014-09-04

申请号：US14148470

申请日：2014-01-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US20130342240A1

公开(公告)日：2013-12-26

申请号：US13915290

申请日：2013-06-11

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H03K5/24

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.