公开(公告)号：US08502559B2

公开(公告)日：2013-08-06

申请号：US13298389

申请日：2011-11-17

Applicant: Rajesh Narwal

Inventor： Rajesh Narwal

IPC: H03L5/00 ,  H03K19/0175

CPC classification number: H03K19/018521

Abstract: A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.

Abstract translation: 电路具有被配置为接收具有第一值的周期性信号的输入。 当所述周期信号具有上升沿时，提供第一电路以产生脉冲，当所述周期信号具有下降沿时，提供脉冲。 第二电路被配置为接收所述脉冲并响应于此提供输出信号，所述输出信号具有与所述输入信号相同的占空比并且具有第二值。

公开(公告)号：US20130127514A1

公开(公告)日：2013-05-23

申请号：US13298389

申请日：2011-11-17

Applicant: Rajesh Narwal

Inventor： Rajesh Narwal

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.

Abstract translation: 电路具有被配置为接收具有第一值的周期性信号的输入。 当所述周期信号具有上升沿时，提供第一电路以产生脉冲，当所述周期信号具有下降沿时，提供脉冲。 第二电路被配置为接收所述脉冲并响应于此提供输出信号，所述输出信号具有与所述输入信号相同的占空比并且具有第二值。

公开(公告)号：US07064595B2

公开(公告)日：2006-06-20

申请号：US11018275

申请日：2004-12-21

Applicant: Manoj Kumar Sharma ,  Sunil Chandra Kasanyal ,  Rajesh Narwal

Inventor： Manoj Kumar Sharma ,  Sunil Chandra Kasanyal ,  Rajesh Narwal

IPC: H03K3/12

CPC classification number: H04L25/0292 ,  H03K3/3565 ,  H03K5/084 ,  H04L25/0272

Abstract: The differential input receiver provides constant symmetrical hysteresis over a wide input signal range. The differential input receiver includes a pair of complementary differential comparators having common input terminals, a pair of series connected complementary current mirrors each having source terminals driven by the output terminals of the corresponding differential comparator, a pair of transistors connected in series across each differential pair transistor in each differential comparator to form a potential divider across it, and a pair of series connected inverting buffers connected to a common output of the differential comparators to provide the final output. The individual buffer outputs are fed back to the control terminals of the series connected transistors in a manner that provides positive feedback thereby providing equal rise-time, fall-delay and transition times in the output signal.

Abstract translation: 差分输入接收器在宽输入信号范围内提供恒定的对称滞后。 差分输入接收机包括一对具有公共输入端的互补差分比较器，一对串联连接的互补电流镜，每个具有由相应的差分比较器的输出端驱动的源极端子，一对晶体管串联连接在每个差分对上 晶体管在每个差分比较器中形成分压器，并且一对串联连接的反相缓冲器连接到差分比较器的公共输出端以提供最终输出。 单个缓冲器输出以提供正反馈的方式反馈到串联连接的晶体管的控制端，从而在输出信号中提供相等的上升时间，下降延迟和转换时间。

公开(公告)号：US06856179B2

公开(公告)日：2005-02-15

申请号：US10662952

申请日：2003-09-12

Applicant: Rajesh Kaushik ,  Rajesh Narwal

Inventor： Rajesh Kaushik ,  Rajesh Narwal

IPC: H03K17/16 ,  H03K3/00

CPC classification number: H03K17/166

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract translation: CMOS输出缓冲器使用来自接地节点的反馈，通过利用可容忍的接地反弹限制来减少接地反弹，使其对工作条件和处理参数的敏感性降低。 输出缓冲器的NMOS器件的输入由从接地节点接收来自预驱动器的第一输入和第二输入（即，反馈）的控制元件的输出提供。