公开(公告)号：US06856179B2

公开(公告)日：2005-02-15

申请号：US10662952

申请日：2003-09-12

Applicant: Rajesh Kaushik ,  Rajesh Narwal

Inventor： Rajesh Kaushik ,  Rajesh Narwal

IPC: H03K17/16 ,  H03K3/00

CPC classification number: H03K17/166

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract translation: CMOS输出缓冲器使用来自接地节点的反馈，通过利用可容忍的接地反弹限制来减少接地反弹，使其对工作条件和处理参数的敏感性降低。 输出缓冲器的NMOS器件的输入由从接地节点接收来自预驱动器的第一输入和第二输入（即，反馈）的控制元件的输出提供。

公开(公告)号：US07613853B2

公开(公告)日：2009-11-03

申请号：US10973812

申请日：2004-10-25

Applicant: Rajat Chauhan ,  Rajesh Kaushik

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: G06F3/00

CPC classification number: H03K3/0375 ,  H04L25/45

Abstract: An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.

Abstract translation: 具有单端和差分信号能力的改进的输出缓冲器，为同步和异步应用的差分输出配置提供对称输出，包括：一对接收互补输入信号的触发器，一对发射器各自具有其输入连接 触发器之一的输出并将其输出提供给输出引脚，感测块感测互补输入信号上的转换并在每个转换时产生脉冲，并且多路复用器的输出连接到时钟输入端 所述一对触发器和一个输入连接到用于异步模式操作的检测块的输出，第二输入连接到用于同步模式操作的时钟信号和使能异步模式或同步模式操作的选择输入。

公开(公告)号：US20050127970A1

公开(公告)日：2005-06-16

申请号：US10993132

申请日：2004-11-18

Applicant: Manoj Sharma ,  Rajesh Kaushik

Inventor： Manoj Sharma ,  Rajesh Kaushik

IPC: H03K3/3565 ,  H03K3/037

CPC classification number: H03K3/3565

Abstract: An Input Output Block (IOB) provides programmable hysteresis to support multiple IO standards including a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signalling, or to a reference voltage for the case of single-ended signalling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a different size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresis that is determined by the combination of selection switches that are enabled and the relative sizes of the corresponding parallel coupled transistors.

Abstract translation: 输入输出块（IOB）提供可编程滞后以支持多个IO标准，包括差分放大器，其中差分放大器具有耦合到输入信号的一个输入，以及在差分信号的情况下耦合到互补输入信号的第二输入，或者参考电压 单端信令的情况，耦合到所述差分放大器的一个输出的一对串联耦合数字反相器，与差分放大器的每个输入晶体管并联耦合的一个或多个晶体管，每个并联耦合组的每个晶体管为 每组中的每个并联耦合晶体管的控制端耦合到所述串联耦合的反相器之一的输出，使得通过选择开关直接或间接地提供正反馈，以及迟滞控制位 对称地启用或禁用每个所述选择开关以提供程序 由能够使能的选择开关的组合和对应的并联耦合晶体管的相对尺寸确定的可能的滞后电平。

公开(公告)号：US07157936B2

公开(公告)日：2007-01-02

申请号：US10347139

申请日：2003-01-17

Applicant: Rajat Chauhan ,  Rajesh Kaushik

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: H01L25/00

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 提供了一种方法和改进的FPGA装置，用于在核心逻辑功能中使得能够选择性地部署IO单元中的未使用的触发器或其他电路元件以及查找表（LUT）中的未使用的解码器或其他电路元件，包括用于 有选择地从IO垫电路或所述LUT电路断开未使用的电路元件，以及连接装置，用于选择性地将所述断开的电路元件连接到核心逻辑的连接矩阵或它们之间，以提供独立配置的功能。

公开(公告)号：US20050174146A1

公开(公告)日：2005-08-11

申请号：US10957318

申请日：2004-10-01

Applicant: Rajat Chauhan ,  Rajesh Kaushik

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: H03K19/0185 ,  H03K19/0175

CPC classification number: H03K19/018585

Abstract: An improved input buffer providing configurable single-ended and differential signaling capability, comprising an input signal comparator, a first pad connected to one input of the comparator. An internal reference voltage source may be connected to one terminal of a first selection switch. The second terminal of the first selection switch is connected to the second input of the comparator and one terminal of a second selection switch is connected to the second input of the comparator. Further, a second input pad is connected to the second terminal of the second selection switch. The invention also includes a mode selector that enables the first selection switch and disables the second selection switch for providing single-ended operation using the internal reference voltage source, or enables the second selection switch and disables the first selection switch for enabling differential operation or single-ended operation using an external voltage reference.

Abstract translation: 一种提供可配置的单端和差分信令能力的改进的输入缓冲器，包括输入信号比较器，连接到比较器的一个输入的第一焊盘。 内部参考电压源可以连接到第一选择开关的一个端子。 第一选择开关的第二端连接到比较器的第二输入端，第二选择开关的一端连接到比较器的第二输入端。 此外，第二输入焊盘连接到第二选择开关的第二端子。 本发明还包括一种模式选择器，其能够使第一选择开关和第二选择开关用于使用内部参考电压源提供单端操作，或启用第二选择开关并禁用第一选择开关以实现差分操作或单个 使用外部参考电压进行操作。

公开(公告)号：US07218147B2

公开(公告)日：2007-05-15

申请号：US10957318

申请日：2004-10-01

Applicant: Rajat Chauhan ,  Rajesh Kaushik

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: H03K19/0175

CPC classification number: H03K19/018585

Abstract: An improved input buffer providing configurable single-ended and differential signaling capability, comprising an input signal comparator, a first pad connected to one input of the comparator. An internal reference voltage source may be connected to one terminal of a first selection switch. The second terminal of the first selection switch is connected to the second input of the comparator and one terminal of a second selection switch is connected to the second input of the comparator. Further, a second input pad is connected to the second terminal of the second selection switch. The invention also includes a mode selector that enables the first selection switch and disables the second selection switch for providing single-ended operation using the internal reference voltage source, or enables the second selection switch and disables the first selection switch for enabling differential operation or single-ended operation using an external voltage reference.

Abstract translation: 一种提供可配置的单端和差分信令能力的改进的输入缓冲器，包括输入信号比较器，连接到比较器的一个输入的第一焊盘。 内部参考电压源可以连接到第一选择开关的一个端子。 第一选择开关的第二端连接到比较器的第二输入端，第二选择开关的一端连接到比较器的第二输入端。 此外，第二输入焊盘连接到第二选择开关的第二端子。 本发明还包括一种模式选择器，其能够使第一选择开关和第二选择开关用于使用内部参考电压源提供单端操作，或启用第二选择开关并禁用第一选择开关以实现差分操作或单个 使用外部参考电压进行操作。

公开(公告)号：US07154318B2

公开(公告)日：2006-12-26

申请号：US10993132

申请日：2004-11-18

Applicant: Manoj Kumar Sharma ,  Rajesh Kaushik

Inventor： Manoj Kumar Sharma ,  Rajesh Kaushik

IPC: H03K3/356

CPC classification number: H03K3/3565

Abstract: An Input Output Block (IOB) provides programmable hysteresis to support multiple IO standards including a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signalling, or to a reference voltage for the case of single-ended signalling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a different size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresis that is determined by the combination of selection switches that are enabled and the relative sizes of the corresponding parallel coupled transistors.

Abstract translation: 输入输出块（IOB）提供可编程滞后以支持多个IO标准，包括差分放大器，其中差分放大器具有耦合到输入信号的一个输入，以及在差分信号的情况下耦合到互补输入信号的第二输入，或者参考电压 单端信令的情况，耦合到所述差分放大器的一个输出的一对串联耦合数字反相器，与差分放大器的每个输入晶体管并联耦合的一个或多个晶体管，每个并联耦合组的每个晶体管为 每组中的每个并联耦合晶体管的控制端耦合到所述串联耦合的反相器之一的输出，使得通过选择开关直接或间接地提供正反馈，以及迟滞控制位 对称地启用或禁用每个所述选择开关以提供程序 由能够使能的选择开关的组合和对应的并联耦合晶体管的相对尺寸确定的可能的滞后电平。

公开(公告)号：US20050146367A1

公开(公告)日：2005-07-07

申请号：US10973812

申请日：2004-10-25

Applicant: Rajat Chauhan ,  Rajesh Kaushik

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: H03K3/037 ,  H04L25/45

CPC classification number: H03K3/0375 ,  H04L25/45

Abstract: An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.

Abstract translation: 具有单端和差分信号能力的改进的输出缓冲器，为同步和异步应用的差分输出配置提供对称输出，包括：一对接收互补输入信号的触发器，一对发射器各自具有其输入连接 触发器之一的输出并将其输出提供给输出引脚，感测块感测互补输入信号上的转换并在每个转换时产生脉冲，并且多路复用器的输出连接到时钟输入 所述一对触发器和一个输入连接到用于异步模式操作的检测块的输出，第二输入连接到用于同步模式操作的时钟信号和使能异步模式或同步模式操作的选择输入。