公开(公告)号：US07680097B1

公开(公告)日：2010-03-16

申请号：US11365214

申请日：2006-02-28

Applicant: Adam Goldstein ,  David Smith ,  Harish Devanagondi ,  Hugh Barrass ,  Kamran Torabi ,  Rajesh Patil

Inventor： Adam Goldstein ,  David Smith ,  Harish Devanagondi ,  Hugh Barrass ,  Kamran Torabi ,  Rajesh Patil

IPC: H04J1/16

CPC classification number: H04L49/101 ,  H04L49/103 ,  H04L49/15 ,  H04L49/45

Abstract: A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and recollect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.

Abstract translation: 具有混合交换机架构的网络交换机，其通过使用多个共享存储交换机结构和多个交叉交换结构来扩展以增加连接性，缓冲和带宽。 每个交叉开关结构耦合到每个共享存储器交换结构。 共享存储交换机结构被配置为存储和检索数据包。 交叉开关结构被配置为向每个共享存储交换机结构分发和重新收集分组。 具有混合交换机结构的网络交换机将分组从交叉交换结构分配到多个共享存储交换机结构，以在多个共享存储交换机结构之间共享分布式分组。

公开(公告)号：US20060206620A1

公开(公告)日：2006-09-14

申请号：US11431444

申请日：2006-05-09

Applicant: Harish Devanagondi ,  Rajesh Patil ,  Sanjeev Mahalawat ,  Jianyong Sun

Inventor： Harish Devanagondi ,  Rajesh Patil ,  Sanjeev Mahalawat ,  Jianyong Sun

IPC: G06F15/16 ,  G06F13/28

CPC classification number: H03M13/09

Abstract: A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an associated exception map in a memory of the apparatus. An exception detector at each processing stage detects whether any exception conditions apply to the data packet at the processing stage, and if so, a bit setter sets, modifies, or resets one or more bits in the exception map associated with exception conditions detected at the processing stage. An exception handler processes the exception map in response to the state of in the exception map after all the processing stages are complete.

公开(公告)号：US07062641B1

公开(公告)日：2006-06-13

申请号：US09758540

申请日：2001-01-10

Applicant: Harish R. Devanagondi ,  Rajesh Patil ,  Sanjeev Mahalawat ,  Jianyong Sun

Inventor： Harish R. Devanagondi ,  Rajesh Patil ,  Sanjeev Mahalawat ,  Jianyong Sun

IPC: G06F7/499

CPC classification number: H03M13/09

Abstract: Unified exception handling may be provided by processing a data packet through at least two pipelined processing stages in a data packet processor such as a switch, router, bridge, or similar network device, each of the data packets having associated with it (while it is being processed) an exception map disposed in a memory of the network device. The bits in the exception map are set, modified, or reset in response to exception conditions detected at the various processing stages. After the packet has been fully processed, an exception handler takes as an input the exception map and further processes the packet in response to the state of the exception map.

Abstract translation: 可以通过在数据分组处理器（例如交换机，路由器，网桥或类似网络设备）中的至少两个流水线处理阶段处理数据分组来提供统一的异常处理，每个数据分组与其相关联 被处理）布置在网络设备的存储器中的异常映射。 响应于在各种处理阶段检测到的异常情况，异常映射中的位被设置，修改或重置。 在数据包被完全处理之后，异常处理程序将异常映射作为输入，并响应于异常映射的状态进一步处理数据包。