公开(公告)号：US20210250207A1

公开(公告)日：2021-08-12

申请号：US17252799

申请日：2019-06-14

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

IPC: H04L25/03

Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (IS I) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of IS I offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the IS I offset for the immediate symbol.

公开(公告)号：US11038725B2

公开(公告)日：2021-06-15

申请号：US16847793

申请日：2020-04-14

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Nhat Nguyen ,  Charles Walter Boecker

IPC: H04L25/49 ,  H04L7/00 ,  H04L7/033 ,  H04L25/03

Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

公开(公告)号：US20210058278A1

公开(公告)日：2021-02-25

申请号：US17045769

申请日：2019-03-25

Applicant: Rambus Inc.

Inventor： Haidang Lin ,  Charles Walter Boecker ,  Masum Hossain

IPC: H04L25/03 ,  H04L25/49

Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.

公开(公告)号：US11646724B2

公开(公告)日：2023-05-09

申请号：US17668584

申请日：2022-02-10

Applicant: Rambus Inc.

Inventor： Charles Walter Boecker ,  Roxanne Vu ,  Eric Douglas Groen

IPC: H03K5/13 ,  H03K3/356 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/13 ,  H03K3/356104 ,  H03K5/135 ,  H03K2005/00019

Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.