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公开(公告)号：US10348480B2
公开(公告)日：2019-07-09
申请号：US15799016
申请日：2017-10-31
申请人： Rambus Inc.
摘要： A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.
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公开(公告)号：US10230384B2
公开(公告)日：2019-03-12
申请号：US15818434
申请日：2017-11-20
申请人： Rambus Inc.
发明人： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
摘要： A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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3.发明申请公开(公告)号：US20220407749A1
公开(公告)日：2022-12-22
申请号：US17852278
申请日：2022-06-28
申请人： Rambus Inc.
IPC分类号： H04L25/03
摘要： A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.
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4.发明申请公开(公告)号：US20210250207A1
公开(公告)日：2021-08-12
申请号：US17252799
申请日：2019-06-14
申请人： Rambus Inc.
IPC分类号： H04L25/03
摘要： A PAM-4 DFE receives an input signal distorted by inter-symbol interference (IS I) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of IS I offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the IS I offset for the immediate symbol.
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公开(公告)号：US11038725B2
公开(公告)日：2021-06-15
申请号：US16847793
申请日：2020-04-14
申请人： Rambus Inc.
摘要： A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US11038514B2
公开(公告)日：2021-06-15
申请号：US16885805
申请日：2020-05-28
申请人： Rambus Inc.
发明人： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
摘要： A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US12074623B2
公开(公告)日：2024-08-27
申请号：US18144342
申请日：2023-05-08
申请人： Rambus Inc.
CPC分类号： H04B1/123 , H04B1/12 , H04L25/0264 , H04L25/03057 , H04L25/03076 , H04L25/03133 , H04L25/4917 , H04L27/00 , H04L27/01 , H04L27/06
摘要： Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US20180167076A1
公开(公告)日：2018-06-14
申请号：US15818434
申请日：2017-11-20
申请人： Rambus Inc.
发明人： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
摘要： A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US20170033918A1
公开(公告)日：2017-02-02
申请号：US15212514
申请日：2016-07-18
申请人： Rambus Inc.
CPC分类号： H04L7/0087 , H03K7/02 , H03L7/00 , H04L7/0025 , H04L7/0337 , H04L25/4917
摘要： A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.
摘要翻译： 接收器串行数据流通过将本地时钟相位对准数据流中的转换，从近似频率参考时钟产生本地定时参考时钟。 这个过程通常被称为时钟和数据恢复（CDR）。 选择数据信号的某些转换用于对准本地时钟，并忽略某些转换。 来自接收多个串行数据流的多个接收机的相位误差信号被组合并用于对频率参考时钟进行共同的相位调整。 这些通用调整跟踪所接收数据流通用的抖动。 使用本地相位误差信号来进行使各个本地时钟更好地对准其相应串行数据流的转换的本地调整。 这些本地调整跟踪每个相应串行数据流更独特的抖动。
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10.发明授权公开(公告)号：US11770275B2
公开(公告)日：2023-09-26
申请号：US17852278
申请日：2022-06-28
申请人： Rambus Inc.
IPC分类号： H04L25/03
CPC分类号： H04L25/03057
摘要： A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.
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