公开(公告)号：US20230006869A1

公开(公告)日：2023-01-05

申请号：US17864100

申请日：2022-07-13

Applicant: Rambus Inc.

Inventor： Kamran Farzan ,  Dongyun Lee

IPC: H04L27/04 ,  H04L27/08

Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.

公开(公告)号：US20220405016A1

公开(公告)日：2022-12-22

申请号：US17833657

申请日：2022-06-06

Applicant: Rambus Inc.

Inventor： Dongyun Lee

IPC: G06F3/06

Abstract: Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.

公开(公告)号：US12292601B2

公开(公告)日：2025-05-06

申请号：US17963065

申请日：2022-10-10

Applicant: Rambus Inc.

Inventor： Mark D. Kellam ,  Dongyun Lee ,  Thomas Vogelsang ,  Steven C. Woo

IPC: G02B6/293 ,  G02B6/12 ,  H04B10/50

Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

公开(公告)号：US12287712B2

公开(公告)日：2025-04-29

申请号：US18059900

申请日：2022-11-29

Applicant: Rambus Inc.

Inventor： Joohee Kim ,  Dongyun Lee

IPC: G11C11/4093 ,  G06F11/20 ,  G11C29/00 ,  H01L23/00 ,  H01L25/065

Abstract: Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.

公开(公告)号：US20250124273A1

公开(公告)日：2025-04-17

申请号：US18930209

申请日：2024-10-29

Applicant: Rambus Inc.

Inventor： Dongyun Lee ,  Brent S. Haukness

IPC: G06N3/065 ,  G06F7/544 ,  G06F17/16 ,  G06J1/00

Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

公开(公告)号：US20250021270A1

公开(公告)日：2025-01-16

申请号：US18779269

申请日：2024-07-22

Applicant: Rambus Inc.

Inventor： Dongyun Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093

Abstract: Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.

公开(公告)号：US12165047B2

公开(公告)日：2024-12-10

申请号：US17424254

申请日：2020-01-23

Applicant: Rambus Inc.

Inventor： Dongyun Lee ,  Brent S. Haukness

IPC: G06N3/065 ,  G06F7/544 ,  G06F17/16 ,  G06J1/00

Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.

公开(公告)号：US20240393982A1

公开(公告)日：2024-11-28

申请号：US18794161

申请日：2024-08-05

Applicant: Rambus Inc.

Inventor： Dongyun Lee ,  Steven C. Woo

IPC: G06F3/06

Abstract: A memory module supports multiple memory channel modes, each including a double-date-rate (DDR) data channel supported by an independent command-and-address (CA) channel. In a two-channel mode, the memory module supports two DDR data channels using two respective DDR CA channels. Each CA channel includes a corresponding set of CA links. In a four-channel mode, the memory module supports two pairs of DDR data channels, each pair supported by a pair of independent CA channels. Memory commands issued in the four-channel mode are time interleaved to share one of the sets of CA links.

公开(公告)号：US20220413768A1

公开(公告)日：2022-12-29

申请号：US17832802

申请日：2022-06-06

Applicant: Rambus Inc.

Inventor： Dongyun Lee ,  Steven C. Woo

IPC: G06F3/06

Abstract: A memory module supports multiple memory channel modes, each including a double-date-rate (DDR) data channel supported by an independent command-and-address (CA) channel. In a two-channel mode, the memory module supports two DDR data channels using two respective DDR CA channels. Each CA channel includes a corresponding set of CA links. In a four-channel mode, the memory module supports two pairs of DDR data channels, each pair supported by a pair of independent CA channels. Memory commands issued in the four-channel mode are time interleaved to share one of the sets of CA links.

公开(公告)号：US20220114431A1

公开(公告)日：2022-04-14

申请号：US17424254

申请日：2020-01-23

Applicant: Rambus Inc.

Inventor： Dongyun Lee ,  Brent S. Haukness

IPC: G06N3/063 ,  G06J1/00

Abstract: An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of input value. The multiply-adder circuitry generates a matrix of analog output signals by convolving the matrix of digital-weight values with the matrix of analog input signals including, for each analog output signal within the matrix of analog output signals, switchably enabling weighted current contributions to the analog output signal based on logic states of on respective bits of one or more of the digital-weight values.