公开(公告)号：US20150372804A1

公开(公告)日：2015-12-24

申请号：US14722995

申请日：2015-05-27

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04L7/00 ,  H04L1/20

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract translation: 集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。 可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试 时钟代替参考时钟，同时在其输入端接收测试数据序列。 接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟 ，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。

公开(公告)号：US09071407B2

公开(公告)日：2015-06-30

申请号：US13846491

申请日：2013-03-18

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04B3/46 ,  H04L7/00 ,  H04L7/10 ,  G01R31/317 ,  H04L1/20 ,  H04L1/24

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract translation: 集成电路包括多个接收器，每个接收器具有时钟和数据恢复电路。 可以使第一接收机中的第一本地时钟恢复电路产生模拟要测试的条件的测试时钟，并且使包括第二本地时钟恢复电路在内的多个接收机中的第二接收机使用该测试 时钟代替参考时钟，同时在其输入端接收测试数据序列。 接收机中的时钟和数据恢复电路可以包括响应于环路控制信号的时钟控制环路，以响应于（i）用于正常操作或在测试期间的相应数据信号中的选择性的一个来选择性地修改所选择的参考时钟以产生本地时钟 ，以及（ii）施加到时钟控制回路的测试信号，在这种情况下产生测试时钟。

公开(公告)号：US20140253195A1

公开(公告)日：2014-09-11

申请号：US14165370

申请日：2014-01-27

Applicant: RAMBUS INC.

Inventor： Srinivasaraman Chandrasekaran ,  Gundlapalli Shanmukha Srinivas

IPC: H03K5/156

CPC classification number: H03K5/1565

Abstract: A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.

Abstract translation: 相位插值器（PI）可以用作发送路径中的精确控制的延迟元件，例如在时钟转发的串行链路中。 公开了用于估计校正所接收时钟的占空比和/或相位误差所需的延迟的方法和电路。 这些校正或增量值可以被发送回发射机侧，优选地以PI相位代码直接表示，以便在发射机时钟电路中进行便利的调整。 公开了用于测量和减轻对PI积分非线性的影响的各种技术。