公开(公告)号：US20230367480A1

公开(公告)日：2023-11-16

申请号：US18064442

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun Yoon

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679

Abstract: A memory device includes a memory cell array having memory cells therein that are programed to a plurality of program states, and a page buffer circuit having a plurality of page buffers therein that are connected to a plurality of bit lines associated with the memory cell array. Each of the page buffers includes a sensing latch that is connected to a corresponding one of the plurality of bit lines, and is configured to control a precharge operation performed on a corresponding bit line. Control logic is provided to control a verification operation performed on the plurality of program states within the memory cells by controlling the page buffer circuit, a plurality of dump operations on the sensing latch, which are based on values of at least two bits stored in each of the page buffers, and a selective precharge of bit lines that are connected to memory cells to be programmed to a first program state to be verified, from among the plurality of program states.

公开(公告)号：US20200319953A1

公开(公告)日：2020-10-08

申请号：US16708988

申请日：2019-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejin Kim ,  Hyunjun Yoon

IPC: G06F11/07 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/4093 ,  G11C11/4074 ,  G11C7/10

Abstract: A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.