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公开(公告)号：US20180173836A1
公开(公告)日：2018-06-21
申请号：US15896415
申请日：2018-02-14
发明人： TAEJOONG SONG , SANGHOON BAEK , SUNGWE CHO , JUNG-HO DO , GIYOUNG YANG , JINYOUNG LIM
IPC分类号： G06F17/50 , H01L27/118 , H01L27/02
CPC分类号： G06F17/5077 , H01L27/0207 , H01L27/11807
摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
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公开(公告)号：US20200152640A1
公开(公告)日：2020-05-14
申请号：US16725155
申请日：2019-12-23
发明人： JUNG-HO DO , SEUNGYOUNG LEE , JONGHOON JUNG , JINYOUNG LIM , GIYOUNG YANG , SANGHOON BAEK , TAEJOONG SONG
IPC分类号： H01L27/11 , H01L23/522 , H01L49/02 , H01L21/768
摘要： A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
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公开(公告)号：US20190252297A1
公开(公告)日：2019-08-15
申请号：US16394961
申请日：2019-04-25
发明人： JUNG-HO DO , TAE-JOONG SONG , SEUNG-YOUNG LEE , JONG-HOON JUNG
IPC分类号： H01L23/48 , G06F17/50 , H01L23/482 , H01L27/02 , H01L27/118
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：US20180323082A1
公开(公告)日：2018-11-08
申请号：US16032127
申请日：2018-07-11
发明人： JUNG-HO DO , JONGHOON JUNG , SANGHOON BAEK , SEUNGYOUNG LEE , TAEJOONG SONG , JINYOUNG LIM
IPC分类号： H01L21/3213 , H01L21/8238
CPC分类号： H01L21/32139 , H01L21/823807 , H01L21/823821 , H01L21/823878
摘要： A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.
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公开(公告)号：US20180226323A1
公开(公告)日：2018-08-09
申请号：US15865941
申请日：2018-01-09
发明人： JUNG-HO DO , TAE-JOONG SONG , SEUNG-YOUNG LEE , JONG-HOON JUNG
IPC分类号： H01L23/48 , G06F17/50 , H01L23/482
CPC分类号： H01L23/481 , G06F17/5072 , G06F17/5077 , H01L23/482 , H01L27/0207
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：US20170148727A1
公开(公告)日：2017-05-25
申请号：US15355159
申请日：2016-11-18
发明人： JUNG-HO DO , SEUNGYOUNG LEE , JONGHOON JUNG , JINYOUNG LIM , GIYOUNG YANG , SANGHOON BAEK , TAEJOONG SONG
IPC分类号： H01L23/528 , H01L23/532 , H01L27/11 , H01L23/522
摘要： A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
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公开(公告)号：US20170148687A1
公开(公告)日：2017-05-25
申请号：US15350716
申请日：2016-11-14
发明人： JUNG-HO DO , JONGHOON JUNG , SANGHOON BAEK , SEUNGYOUNG LEE , TAEJOONG SONG , JINYOUNG LIM
IPC分类号： H01L21/8238 , H01L21/3213
CPC分类号： H01L21/32139 , H01L21/823807 , H01L21/823821 , H01L21/823878
摘要： A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.
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公开(公告)号：US20160254256A1
公开(公告)日：2016-09-01
申请号：US15046200
申请日：2016-02-17
发明人： SANGHOON BAEK , JUNG-HO DO , TAEJOONG SONG , GIYOUNG YANG , SEUNGYOUNG LEE , JINYOUNG LIM
IPC分类号： H01L27/02 , H01L23/522 , H01L27/088 , H01L23/528
CPC分类号： H01L27/0207 , H01L23/5226 , H01L23/5283 , H01L27/088 , H01L27/092 , H01L27/1104
摘要： A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.
摘要翻译： 芯片上系统装置可以包括具有有源图案的衬底，与有源图案交叉并且沿第一方向延伸的栅极电极以及电连接到有源图案和栅电极的第一金属层。 第一金属层可以包括沿第一方向延伸的第一金属线和在第一方向上与第一金属线隔开的第二金属线，以沿与第一方向交叉的第二方向延伸。 第一和第二金属线可以包括平行于第二方向的第一和第二侧壁，第一和第二侧壁可以彼此面对，并且第一侧壁可以具有最小线宽度的两倍或三倍的长度。
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