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公开(公告)号：US20210057310A1
公开(公告)日：2021-02-25
申请号：US17075141
申请日：2020-10-20
发明人： JUNG-HO DO , TAE-JOONG SONG , SEUNG-YOUNG LEE , JONG-HOON JUNG
IPC分类号： H01L23/48 , H01L23/482 , H01L27/02 , H01L27/118 , H01L23/485 , H01L21/768 , G06F30/394
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：US20180173835A1
公开(公告)日：2018-06-21
申请号：US15689008
申请日：2017-08-29
发明人： JUNG-HO DO , Jong-Hoon Jung , Seung-Young Lee , Tae-Joong Song
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/70 , G03F7/70283 , G03F7/70466 , G06F17/5009 , G06F17/5068 , G06F17/5081
摘要： An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
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3.发明公开公开(公告)号：US20240203974A1
公开(公告)日：2024-06-20
申请号：US18596731
申请日：2024-03-06
发明人： JUNG-HO DO , DAL-HEE LEE , JIN-YOUNG LIM , TAE-JOONG SONG , JONG-HOON JUNG
IPC分类号： H01L27/02 , G06F30/00 , G11C5/06 , G11C8/16 , G11C11/412 , H01L21/768 , H01L27/088 , H01L27/118
CPC分类号： H01L27/0207 , G06F30/00 , G11C5/063 , G11C8/16 , G11C11/412 , H01L21/76895 , H01L27/088 , H01L27/11807 , H01L2027/11875
摘要： An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.
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公开(公告)号：US20230223319A1
公开(公告)日：2023-07-13
申请号：US18123296
申请日：2023-03-19
发明人： JUNG-HO DO , TAE-JOONG SONG , SEUNG-YOUNG LEE , JONG-HOON JUNG
IPC分类号： H01L23/48 , H01L27/02 , G06F30/394 , H01L23/482 , H01L23/485 , H01L21/768 , H01L27/118 , G06F30/392
CPC分类号： H01L23/481 , H01L27/0207 , G06F30/394 , H01L23/482 , H01L23/485 , H01L21/76895 , H01L27/11807 , G06F30/392 , H01L2027/11875
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：US20180174861A1
公开(公告)日：2018-06-21
申请号：US15899686
申请日：2018-02-20
发明人： JUNG-HO DO , JONGHOON JUNG , SANGHOON BAEK , SEUNGYOUNG LEE , TAEJOONG SONG , JINYOUNG LIM
IPC分类号： H01L21/3213 , H01L21/8238
CPC分类号： H01L21/32139 , H01L21/823807 , H01L21/823821 , H01L21/823878
摘要： A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.
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公开(公告)号：US20230207429A1
公开(公告)日：2023-06-29
申请号：US18119560
申请日：2023-03-09
发明人： JUNG-HO DO , TAE-JOONG SONG , SEUNG-YOUNG LEE , JONG-HOON JUNG
IPC分类号： H01L23/48 , H01L23/482 , H01L27/02 , H01L27/118 , H01L23/485 , H01L21/768 , G06F30/394
CPC分类号： H01L23/481 , G06F30/394 , H01L21/76895 , H01L23/482 , H01L23/485 , H01L27/0207 , H01L27/11807 , G06F30/392 , H01L2027/11875
摘要： An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
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公开(公告)号：US20180182846A1
公开(公告)日：2018-06-28
申请号：US15820053
申请日：2017-11-21
发明人： MYOUNG-HO KANG , JUNG-HO DO , GIYOUNG YANG , SEUNGYOUNG LEE
IPC分类号： H01L29/06 , H01L27/092 , H01L29/08 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/0653 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0847 , H01L29/165 , H01L29/78 , H01L29/7848
摘要： A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.
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公开(公告)号：US20160056083A1
公开(公告)日：2016-02-25
申请号：US14833922
申请日：2015-08-24
发明人： JUNG-HO DO , SANGHOON BAEK , SUNYOUNG PARK , SANG-KYU OH , JINTAE KIM , HYOSIG WON
IPC分类号： H01L21/8234 , H01L21/027 , H01L29/66 , H01L29/417 , H01L21/321 , H01L21/28 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/0274 , H01L21/28008 , H01L21/32115 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L29/41758 , H01L29/66568
摘要： A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.
摘要翻译： 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在器件中比第一触点的顶表面的水平低的水平面上。
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公开(公告)号：US20200334407A1
公开(公告)日：2020-10-22
申请号：US16915369
申请日：2020-06-29
发明人： JIN-TAE KIM , JUNG-HO DO , TAE-JOONG SONG , DOO-HEE CHO , SEUNG-YOUNG LEE
IPC分类号： G06F30/394 , G06F30/392
摘要： A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.
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公开(公告)号：US20190267366A1
公开(公告)日：2019-08-29
申请号：US16407919
申请日：2019-05-09
发明人： JUNG-HO DO , Woojin Rim , Jisu Yu , Jonghoon Jung
IPC分类号： H01L27/02 , H01L27/092 , H01L23/528 , G03F1/36 , H01L23/522 , G06F17/50 , H01L27/118 , H01L21/8238 , H01L23/485
摘要： A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.
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