公开(公告)号：US20240038873A1

公开(公告)日：2024-02-01

申请号：US18483413

申请日：2023-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok Suh ,  Daewon Kim ,  Beomjin Park ,  Sukhyung Park ,  Sungil Park ,  Jaehoon Shin ,  Bongseob Yang ,  Junggun You ,  Jaeyun Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/78696 ,  H01L29/66553 ,  H01L29/7727

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

公开(公告)号：US11430808B2

公开(公告)日：2022-08-30

申请号：US16895364

申请日：2020-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Beyounghyun Koh ,  Yongjin Kwon ,  Kangmin Kim ,  Jaehoon Shin ,  JoongShik Shin ,  Sungsoo Ahn ,  Seunghwan Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.