公开(公告)号：US20170070214A1

公开(公告)日：2017-03-09

申请号：US15253270

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SAN-HA KIM ,  MIN-SU KIM ,  MATTHEW BERZINS

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/356121

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

Abstract translation: 半导体电路包括第一电路和第二电路。 第一电路基于输入数据的逻辑电平，时钟信号的逻辑电平和第一节点的逻辑电平来确定第二节点的逻辑电平和第三节点的逻辑电平。 第二电路基于时钟信号的逻辑电平来确定第一节点的逻辑电平，第二节点的逻辑电平和第三节点的逻辑电平。 第一电路包括子电路和第一晶体管。 第一电路基于输入数据的逻辑电平和第一节点的逻辑电平来确定第二节点的逻辑电平。 第一晶体管被选通到时钟信号的逻辑电平以将第三节点与第二节点连接。